From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: "Joel Stanley" <joel@jms.id.au>, "Cédric Le Goater" <clg@kaod.org>
Cc: Andrew Jeffery <andrew@aj.id.au>,
Peter Maydell <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH] aspeed: Emulate the AST2600A3
Date: Thu, 4 Mar 2021 14:32:29 +0100 [thread overview]
Message-ID: <fa343c1e-6128-2000-2cb0-1231d8285ac2@amsat.org> (raw)
In-Reply-To: <20210304124316.164742-1-joel@jms.id.au>
On 3/4/21 1:43 PM, Joel Stanley wrote:
> This is the latest revision of the ASPEED 2600 SoC.
>
> Reset values are taken from v8 of the datasheet.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---
> include/hw/misc/aspeed_scu.h | 2 ++
> hw/arm/aspeed_ast2600.c | 2 +-
> hw/misc/aspeed_scu.c | 32 +++++++++++++++++++++++++-------
> 3 files changed, 28 insertions(+), 8 deletions(-)
> -#define AST2600_CLK_SEL3 TO_REG(0x310)
> +#define AST2600_CLK_SEL3 TO_REG(0x308)
This register doesn't seem in use, still it would be
nice to mention this fix in the commit description.
next prev parent reply other threads:[~2021-03-04 13:33 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-04 12:43 [PATCH] aspeed: Emulate the AST2600A3 Joel Stanley
2021-03-04 13:32 ` Philippe Mathieu-Daudé [this message]
2021-04-12 15:27 ` Cédric Le Goater
2021-04-12 22:56 ` Andrew Jeffery
2021-04-13 2:27 ` Joel Stanley
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