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[88.21.68.240]) by smtp.gmail.com with ESMTPSA id w12sm6374656wrg.47.2019.09.21.01.50.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 21 Sep 2019 01:50:59 -0700 (PDT) Subject: Re: [PATCH v2 1/2] riscv: hw: Drop "clock-frequency" property of cpu nodes To: Bin Meng , Alistair Francis , Palmer Dabbelt , qemu-devel@nongnu.org, qemu-riscv@nongnu.org References: <1569044491-7875-1-git-send-email-bmeng.cn@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Openpgp: id=89C1E78F601EE86C867495CBA2A3FD6EDEADC0DE; url=http://pgp.mit.edu/pks/lookup?op=get&search=0xA2A3FD6EDEADC0DE Message-ID: Date: Sat, 21 Sep 2019 10:50:58 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: <1569044491-7875-1-git-send-email-bmeng.cn@gmail.com> Content-Language: en-US X-MC-Unique: N0pvUXmKMRmtvgicpA2BHA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 205.139.110.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi Bin, On 9/21/19 7:41 AM, Bin Meng wrote: > The "clock-frequency" property of cpu nodes isn't required. Drop it. >=20 > This is to keep in sync with Linux kernel commit below: > https://patchwork.kernel.org/patch/11133031/ What happens if you run a older kernel that doesn't contain the referenced patch? > Signed-off-by: Bin Meng > Reviewed-by: Alistair Francis >=20 > --- >=20 > Changes in v2: > - drop the one in spike and virt machines too >=20 > hw/riscv/sifive_u.c | 2 -- > hw/riscv/spike.c | 2 -- > hw/riscv/virt.c | 2 -- > include/hw/riscv/sifive_u.h | 1 - > include/hw/riscv/spike.h | 4 ---- > include/hw/riscv/virt.h | 4 ---- > 6 files changed, 15 deletions(-) >=20 > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index 9f8e84b..02dd761 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -151,8 +151,6 @@ static void create_fdt(SiFiveUState *s, const struct = MemmapEntry *memmap, > char *intc =3D g_strdup_printf("/cpus/cpu@%d/interrupt-controlle= r", cpu); > char *isa; > qemu_fdt_add_subnode(fdt, nodename); > - qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", > - SIFIVE_U_CLOCK_FREQ); > /* cpu 0 is the management hart that does not have mmu */ > if (cpu !=3D 0) { > qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv= 48"); > diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c > index d60415d..8bbffbc 100644 > --- a/hw/riscv/spike.c > +++ b/hw/riscv/spike.c > @@ -102,8 +102,6 @@ static void create_fdt(SpikeState *s, const struct Me= mmapEntry *memmap, > char *intc =3D g_strdup_printf("/cpus/cpu@%d/interrupt-controlle= r", cpu); > char *isa =3D riscv_isa_string(&s->soc.harts[cpu]); > qemu_fdt_add_subnode(fdt, nodename); > - qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", > - SPIKE_CLOCK_FREQ); > qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48")= ; > qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); > qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index d36f562..1303061 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -161,8 +161,6 @@ static void create_fdt(RISCVVirtState *s, const struc= t MemmapEntry *memmap, > char *intc =3D g_strdup_printf("/cpus/cpu@%d/interrupt-controlle= r", cpu); > char *isa =3D riscv_isa_string(&s->soc.harts[cpu]); > qemu_fdt_add_subnode(fdt, nodename); > - qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", > - VIRT_CLOCK_FREQ); > qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48")= ; > qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); > qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); > diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h > index e4df298..4850805 100644 > --- a/include/hw/riscv/sifive_u.h > +++ b/include/hw/riscv/sifive_u.h > @@ -75,7 +75,6 @@ enum { > }; > =20 > enum { > - SIFIVE_U_CLOCK_FREQ =3D 1000000000, > SIFIVE_U_HFCLK_FREQ =3D 33333333, > SIFIVE_U_RTCCLK_FREQ =3D 1000000 > }; > diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h > index 03d8703..dc77042 100644 > --- a/include/hw/riscv/spike.h > +++ b/include/hw/riscv/spike.h > @@ -38,10 +38,6 @@ enum { > SPIKE_DRAM > }; > =20 > -enum { > - SPIKE_CLOCK_FREQ =3D 1000000000 > -}; > - > #if defined(TARGET_RISCV32) > #define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV32GCSU_V1_09_1 > #define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0 > diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h > index 6e5fbe5..68978a1 100644 > --- a/include/hw/riscv/virt.h > +++ b/include/hw/riscv/virt.h > @@ -55,10 +55,6 @@ enum { > VIRTIO_NDEV =3D 0x35 /* Arbitrary maximum number of interrupts */ > }; > =20 > -enum { > - VIRT_CLOCK_FREQ =3D 1000000000 > -}; > - > #define VIRT_PLIC_HART_CONFIG "MS" > #define VIRT_PLIC_NUM_SOURCES 127 > #define VIRT_PLIC_NUM_PRIORITIES 7 >=20