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[88.21.103.182]) by smtp.gmail.com with ESMTPSA id e18sm2114137wrr.95.2019.12.02.22.19.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 02 Dec 2019 22:19:46 -0800 (PST) Subject: Re: [PATCH v2 3/4] target/arm: Prepare generic timer for per-platform CNTFRQ To: Andrew Jeffery , qemu-arm@nongnu.org References: <20191203041440.6275-1-andrew@aj.id.au> <20191203041440.6275-4-andrew@aj.id.au> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Tue, 3 Dec 2019 07:19:45 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191203041440.6275-4-andrew@aj.id.au> Content-Language: en-US X-MC-Unique: lF1CucpqNYehom-5C91Z2A-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: joel@jms.id.au, peter.maydell@linaro.org, Richard Henderson , qemu-devel@nongnu.org, clg@kaod.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 12/3/19 5:14 AM, Andrew Jeffery wrote: > The ASPEED AST2600 clocks the generic timer at the rate of HPLL. On > recent firmwares this is at 1125MHz, which is considerably quicker than > the assumed 62.5MHz of the current generic timer implementation. The > delta between the value as read from CNTFRQ and the true rate of the > underlying QEMUTimer leads to sticky behaviour in AST2600 guests. >=20 > Add a feature-gated property exposing CNTFRQ for ARM CPUs providing the > generic timer. This allows platforms to configure CNTFRQ (and the > associated QEMUTimer) to the appropriate frequency prior to starting the > guest. >=20 > As the platform can now determine the rate of CNTFRQ we're exposed to > limitations of QEMUTimer that didn't previously materialise: In the > course of emulation we need to arbitrarily and accurately convert > between guest ticks and time, but we're constrained by QEMUTimer's use > of an integer scaling factor. The effect is QEMUTimer cannot exactly > capture the period of frequencies that do not cleanly divide > NANOSECONDS_PER_SECOND for scaling ticks to time. As such, provide an > equally inaccurate scaling factor for scaling time to ticks so at least > a self-consistent inverse relationship holds. >=20 > Signed-off-by: Andrew Jeffery > Reviewed-by: Richard Henderson > --- > target/arm/cpu.c | 43 +++++++++++++++++++++++++++++++++---------- > target/arm/cpu.h | 18 ++++++++++++++++++ > target/arm/helper.c | 9 ++++++++- > 3 files changed, 59 insertions(+), 11 deletions(-) >=20 > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index 5698a74061bb..f186019a77fd 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -974,10 +974,12 @@ static void arm_cpu_initfn(Object *obj) > if (tcg_enabled()) { > cpu->psci_version =3D 2; /* TCG implements PSCI 0.2 */ > } > - > - cpu->gt_cntfrq =3D NANOSECONDS_PER_SECOND / GTIMER_SCALE; > } > =20 > +static Property arm_cpu_gt_cntfrq_property =3D > + DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq, > + NANOSECONDS_PER_SECOND / GTIMER_SCALE); > + > static Property arm_cpu_reset_cbar_property =3D > DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); > =20 > @@ -1174,6 +1176,11 @@ void arm_cpu_post_init(Object *obj) > =20 > qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, > &error_abort); > + > + if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { > + qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_propert= y, > + &error_abort); > + } > } > =20 > static void arm_cpu_finalizefn(Object *obj) > @@ -1253,14 +1260,30 @@ static void arm_cpu_realizefn(DeviceState *dev, E= rror **errp) > } > } > =20 > - cpu->gt_timer[GTIMER_PHYS] =3D timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_= SCALE, > - arm_gt_ptimer_cb, cpu); > - cpu->gt_timer[GTIMER_VIRT] =3D timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_= SCALE, > - arm_gt_vtimer_cb, cpu); > - cpu->gt_timer[GTIMER_HYP] =3D timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_S= CALE, > - arm_gt_htimer_cb, cpu); > - cpu->gt_timer[GTIMER_SEC] =3D timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_S= CALE, > - arm_gt_stimer_cb, cpu); > + > + { > + uint64_t scale; Apparently you have to use this odd indent due to the '#ifndef=20 CONFIG_USER_ONLY'. Well, acceptable. > + > + if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { > + if (!cpu->gt_cntfrq) { > + error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", > + cpu->gt_cntfrq); > + return; > + } > + scale =3D gt_cntfrq_period_ns(cpu); > + } else { > + scale =3D GTIMER_SCALE; > + } > + > + cpu->gt_timer[GTIMER_PHYS] =3D timer_new(QEMU_CLOCK_VIRTUAL, sca= le, > + arm_gt_ptimer_cb, cpu); > + cpu->gt_timer[GTIMER_VIRT] =3D timer_new(QEMU_CLOCK_VIRTUAL, sca= le, > + arm_gt_vtimer_cb, cpu); > + cpu->gt_timer[GTIMER_HYP] =3D timer_new(QEMU_CLOCK_VIRTUAL, scal= e, > + arm_gt_htimer_cb, cpu); > + cpu->gt_timer[GTIMER_SEC] =3D timer_new(QEMU_CLOCK_VIRTUAL, scal= e, > + arm_gt_stimer_cb, cpu); > + } > #endif > =20 > cpu_exec_realizefn(cs, &local_err); > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 666c03871fdf..0bcd13dcac81 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -939,6 +939,24 @@ struct ARMCPU { > =20 > static inline unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) > { > + /* > + * The exact approach to calculating guest ticks is: > + * > + * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfr= q, > + * NANOSECONDS_PER_SECOND); > + * > + * We don't do that. Rather we intentionally use integer division > + * truncation below and in the caller for the conversion of host mon= otonic > + * time to guest ticks to provide the exact inverse for the semantic= s of > + * the QEMUTimer scale factor. QEMUTimer's scale facter is an intege= r, so > + * it loses precision when representing frequencies where > + * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to > + * provide an exact inverse leads to scheduling timers with negative > + * periods, which in turn leads to sticky behaviour in the guest. > + * > + * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale= factor > + * cannot become zero. > + */ This comment belong to the previous patch. I'd rather see this function=20 + big comment in target/arm/cpu.c. With comment moved (and if possible function uninlined): Reviewed-by: Philippe Mathieu-Daud=C3=A9 > /* XXX: Could include qemu/timer.h to get NANOSECONDS_PER_SECOND? *= / > const unsigned int ns_per_s =3D 1000 * 1000 * 1000; > return ns_per_s > cpu->gt_cntfrq ? ns_per_s / cpu->gt_cntfrq : 1; > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 2622a9a8d02f..da960d17040b 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -2683,6 +2683,13 @@ void arm_gt_stimer_cb(void *opaque) > gt_recalc_timer(cpu, GTIMER_SEC); > } > =20 > +static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *op= aque) > +{ > + ARMCPU *cpu =3D env_archcpu(env); > + > + cpu->env.cp15.c14_cntfrq =3D cpu->gt_cntfrq; > +} > + > static const ARMCPRegInfo generic_timer_cp_reginfo[] =3D { > /* Note that CNTFRQ is purely reads-as-written for the benefit > * of software; writing it doesn't actually change the timer freque= ncy. > @@ -2697,7 +2704,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[= ] =3D { > .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 0, .opc2 =3D 0, > .access =3D PL1_RW | PL0_R, .accessfn =3D gt_cntfrq_access, > .fieldoffset =3D offsetof(CPUARMState, cp15.c14_cntfrq), > - .resetvalue =3D (1000 * 1000 * 1000) / GTIMER_SCALE, > + .resetfn =3D arm_gt_cntfrq_reset, > }, > /* overall control: mostly access permissions */ > { .name =3D "CNTKCTL", .state =3D ARM_CP_STATE_BOTH, >=20