From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org
Subject: Re: [PATCH 03/13] accel/tcg: Store some tlb flags in CPUTLBEntryFull
Date: Sun, 5 Mar 2023 10:20:17 -0800 [thread overview]
Message-ID: <fc6aae1a-8425-be5e-40b4-f3abc6536b9d@linaro.org> (raw)
In-Reply-To: <CAFEAcA9jhHX7r9FcB8ZyGimN3XGLX=rEONC3jYK=n2JTmj+SSg@mail.gmail.com>
On 3/3/23 08:45, Peter Maydell wrote:
>> +
>> + if (wp_flags & BP_MEM_WRITE) {
>> + write_flags |= TLB_WATCHPOINT;
>> + }
>> + tlb_set_compare(full, &tn, vaddr_page, write_flags, MMU_DATA_STORE,
>> + (prot & PAGE_WRITE) && !(prot & PAGE_WRITE_INV));
>
> So in the old code, if PAGE_WRITE_INV then we set up the
> addr_write field as normal, it just also has the TLB_INVALID_MASK bit
> set. In the new code we won't do that, we'll set addr_write to -1.
Gah. I must have had some sort of rebase fumble, because I know I fixed this, and the
WRITE_INV test should be above, not in the predicate.
r~
next prev parent reply other threads:[~2023-03-05 18:21 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-23 20:43 [PATCH 00/13] {tcg,aarch64}: Add TLB_CHECK_ALIGNED Richard Henderson
2023-02-23 20:43 ` [PATCH 01/13] target/sparc: Use tlb_set_page_full Richard Henderson
2023-02-23 21:25 ` Philippe Mathieu-Daudé
2023-03-01 16:37 ` Mark Cave-Ayland
2023-02-23 20:43 ` [PATCH 02/13] accel/tcg: Retain prot flags from tlb_fill Richard Henderson
2023-03-03 16:29 ` Peter Maydell
2023-02-23 20:43 ` [PATCH 03/13] accel/tcg: Store some tlb flags in CPUTLBEntryFull Richard Henderson
2023-03-03 16:45 ` Peter Maydell
2023-03-05 18:20 ` Richard Henderson [this message]
2023-02-23 20:43 ` [PATCH 04/13] accel/tcg: Honor TLB_DISCARD_WRITE in atomic_mmu_lookup Richard Henderson
2023-03-03 16:46 ` Peter Maydell
2023-02-23 20:43 ` [PATCH 05/13] softmmu/physmem: Check watchpoints for read+write at once Richard Henderson
2023-02-23 21:27 ` Philippe Mathieu-Daudé
2023-02-23 20:43 ` [PATCH 06/13] accel/tcg: Trigger watchpoints from atomic_mmu_lookup Richard Henderson
2023-03-03 16:49 ` Peter Maydell
2023-02-23 20:43 ` [PATCH 07/13] accel/tcg: Move TLB_WATCHPOINT to TLB_SLOW_FLAGS_MASK Richard Henderson
2023-03-03 16:53 ` Peter Maydell
2023-02-23 20:43 ` [PATCH 08/13] target/arm: Support 32-byte alignment in pow2_align Richard Henderson
2023-03-03 16:54 ` Peter Maydell
2023-02-23 20:43 ` [PATCH 09/13] exec/memattrs: Remove target_tlb_bit* Richard Henderson
2023-02-23 21:30 ` Philippe Mathieu-Daudé
2023-02-23 20:43 ` [PATCH 10/13] accel/tcg: Add tlb_fill_flags to CPUTLBEntryFull Richard Henderson
2023-02-23 21:32 ` Philippe Mathieu-Daudé
2023-02-23 20:43 ` [PATCH 11/13] accel/tcg: Add TLB_CHECK_ALIGNED Richard Henderson
2023-02-23 20:43 ` [PATCH 12/13] target/arm: Do memory type alignment check when translation disabled Richard Henderson
2023-02-23 21:41 ` Philippe Mathieu-Daudé
2023-02-23 20:43 ` [PATCH 13/13] target/arm: Do memory type alignment check when translation enabled Richard Henderson
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