* [PATCH] hw/ppc/prep: Remove the deprecated "prep" machine and the OpenHackware BIOS
@ 2019-12-03 7:29 Thomas Huth
2019-12-03 7:45 ` Philippe Mathieu-Daudé
2020-01-07 9:22 ` Thomas Huth
0 siblings, 2 replies; 12+ messages in thread
From: Thomas Huth @ 2019-12-03 7:29 UTC (permalink / raw)
To: qemu-devel, David Gibson, Hervé Poussineau; +Cc: Laurent Vivier
It's been deprecated since QEMU v3.1. The 40p machine should be
used nowadays instead.
Signed-off-by: Thomas Huth <thuth@redhat.com>
---
.gitmodules | 3 -
MAINTAINERS | 1 -
Makefile | 2 +-
docs/interop/firmware.json | 3 +-
hw/ppc/ppc.c | 18 --
hw/ppc/prep.c | 384 +------------------------------------
include/hw/ppc/ppc.h | 1 -
pc-bios/README | 3 -
pc-bios/ppc_rom.bin | Bin 1048576 -> 0 bytes
qemu-deprecated.texi | 6 -
qemu-doc.texi | 15 +-
roms/openhackware | 1 -
tests/boot-order-test.c | 25 ---
tests/cdrom-test.c | 2 +-
tests/endianness-test.c | 2 +-
15 files changed, 10 insertions(+), 456 deletions(-)
delete mode 100644 pc-bios/ppc_rom.bin
delete mode 160000 roms/openhackware
diff --git a/.gitmodules b/.gitmodules
index 19792c9a11..9c0501a4d4 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -10,9 +10,6 @@
[submodule "roms/openbios"]
path = roms/openbios
url = https://git.qemu.org/git/openbios.git
-[submodule "roms/openhackware"]
- path = roms/openhackware
- url = https://git.qemu.org/git/openhackware.git
[submodule "roms/qemu-palcode"]
path = roms/qemu-palcode
url = https://git.qemu.org/git/qemu-palcode.git
diff --git a/MAINTAINERS b/MAINTAINERS
index 5e5e3e52d6..9a9dee0fa4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1081,7 +1081,6 @@ F: hw/dma/i82374.c
F: hw/rtc/m48t59-isa.c
F: include/hw/isa/pc87312.h
F: include/hw/rtc/m48t59.h
-F: pc-bios/ppc_rom.bin
F: tests/acceptance/ppc_prep_40p.py
sPAPR
diff --git a/Makefile b/Makefile
index b437a346d7..86476d1d9e 100644
--- a/Makefile
+++ b/Makefile
@@ -776,7 +776,7 @@ ifdef INSTALL_BLOBS
BLOBS=bios.bin bios-256k.bin bios-microvm.bin sgabios.bin vgabios.bin vgabios-cirrus.bin \
vgabios-stdvga.bin vgabios-vmware.bin vgabios-qxl.bin vgabios-virtio.bin \
vgabios-ramfb.bin vgabios-bochs-display.bin vgabios-ati.bin \
-ppc_rom.bin openbios-sparc32 openbios-sparc64 openbios-ppc QEMU,tcx.bin QEMU,cgthree.bin \
+openbios-sparc32 openbios-sparc64 openbios-ppc QEMU,tcx.bin QEMU,cgthree.bin \
pxe-e1000.rom pxe-eepro100.rom pxe-ne2k_pci.rom \
pxe-pcnet.rom pxe-rtl8139.rom pxe-virtio.rom \
efi-e1000.rom efi-eepro100.rom efi-ne2k_pci.rom \
diff --git a/docs/interop/firmware.json b/docs/interop/firmware.json
index 8ffb7856d2..240f565397 100644
--- a/docs/interop/firmware.json
+++ b/docs/interop/firmware.json
@@ -27,8 +27,7 @@
#
# @openfirmware: The interface is defined by the (historical) IEEE
# 1275-1994 standard. Examples for firmware projects that
-# provide this interface are: OpenBIOS, OpenHackWare,
-# SLOF.
+# provide this interface are: OpenBIOS and SLOF.
#
# @uboot: Firmware interface defined by the U-Boot project.
#
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index 52a18eb7d7..13b6cf85c0 100644
--- a/hw/ppc/ppc.c
+++ b/hw/ppc/ppc.c
@@ -1476,24 +1476,6 @@ int ppc_dcr_init (CPUPPCState *env, int (*read_error)(int dcrn),
}
/*****************************************************************************/
-/* Debug port */
-void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val)
-{
- addr &= 0xF;
- switch (addr) {
- case 0:
- printf("%c", val);
- break;
- case 1:
- printf("\n");
- fflush(stdout);
- break;
- case 2:
- printf("Set loglevel to %04" PRIx32 "\n", val);
- qemu_set_log(val | 0x100);
- break;
- }
-}
PowerPCCPU *ppc_get_vcpu_by_pir(int pir)
{
diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
index 862345c2ac..111cc80867 100644
--- a/hw/ppc/prep.c
+++ b/hw/ppc/prep.c
@@ -42,7 +42,7 @@
#include "hw/loader.h"
#include "hw/rtc/mc146818rtc.h"
#include "hw/isa/pc87312.h"
-#include "hw/net/ne2000-isa.h"
+#include "hw/qdev-properties.h"
#include "sysemu/arch_init.h"
#include "sysemu/kvm.h"
#include "sysemu/qtest.h"
@@ -60,178 +60,9 @@
#define CFG_ADDR 0xf0000510
-#define BIOS_SIZE (1 * MiB)
-#define BIOS_FILENAME "ppc_rom.bin"
#define KERNEL_LOAD_ADDR 0x01000000
#define INITRD_LOAD_ADDR 0x01800000
-/* Constants for devices init */
-static const int ide_iobase[2] = { 0x1f0, 0x170 };
-static const int ide_iobase2[2] = { 0x3f6, 0x376 };
-static const int ide_irq[2] = { 13, 13 };
-
-#define NE2000_NB_MAX 6
-
-static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
-static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
-
-/* ISA IO ports bridge */
-#define PPC_IO_BASE 0x80000000
-
-/* Fake super-io ports for PREP platform (Intel 82378ZB) */
-typedef struct sysctrl_t {
- qemu_irq reset_irq;
- Nvram *nvram;
- uint8_t state;
- uint8_t syscontrol;
- int contiguous_map;
- qemu_irq contiguous_map_irq;
- int endian;
-} sysctrl_t;
-
-enum {
- STATE_HARDFILE = 0x01,
-};
-
-static sysctrl_t *sysctrl;
-
-static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
-{
- sysctrl_t *sysctrl = opaque;
-
- trace_prep_io_800_writeb(addr - PPC_IO_BASE, val);
- switch (addr) {
- case 0x0092:
- /* Special port 92 */
- /* Check soft reset asked */
- if (val & 0x01) {
- qemu_irq_raise(sysctrl->reset_irq);
- } else {
- qemu_irq_lower(sysctrl->reset_irq);
- }
- /* Check LE mode */
- if (val & 0x02) {
- sysctrl->endian = 1;
- } else {
- sysctrl->endian = 0;
- }
- break;
- case 0x0800:
- /* Motorola CPU configuration register : read-only */
- break;
- case 0x0802:
- /* Motorola base module feature register : read-only */
- break;
- case 0x0803:
- /* Motorola base module status register : read-only */
- break;
- case 0x0808:
- /* Hardfile light register */
- if (val & 1)
- sysctrl->state |= STATE_HARDFILE;
- else
- sysctrl->state &= ~STATE_HARDFILE;
- break;
- case 0x0810:
- /* Password protect 1 register */
- if (sysctrl->nvram != NULL) {
- NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
- (k->toggle_lock)(sysctrl->nvram, 1);
- }
- break;
- case 0x0812:
- /* Password protect 2 register */
- if (sysctrl->nvram != NULL) {
- NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
- (k->toggle_lock)(sysctrl->nvram, 2);
- }
- break;
- case 0x0814:
- /* L2 invalidate register */
- // tlb_flush(first_cpu, 1);
- break;
- case 0x081C:
- /* system control register */
- sysctrl->syscontrol = val & 0x0F;
- break;
- case 0x0850:
- /* I/O map type register */
- sysctrl->contiguous_map = val & 0x01;
- qemu_set_irq(sysctrl->contiguous_map_irq, sysctrl->contiguous_map);
- break;
- default:
- printf("ERROR: unaffected IO port write: %04" PRIx32
- " => %02" PRIx32"\n", addr, val);
- break;
- }
-}
-
-static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
-{
- sysctrl_t *sysctrl = opaque;
- uint32_t retval = 0xFF;
-
- switch (addr) {
- case 0x0092:
- /* Special port 92 */
- retval = sysctrl->endian << 1;
- break;
- case 0x0800:
- /* Motorola CPU configuration register */
- retval = 0xEF; /* MPC750 */
- break;
- case 0x0802:
- /* Motorola Base module feature register */
- retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
- break;
- case 0x0803:
- /* Motorola base module status register */
- retval = 0xE0; /* Standard MPC750 */
- break;
- case 0x080C:
- /* Equipment present register:
- * no L2 cache
- * no upgrade processor
- * no cards in PCI slots
- * SCSI fuse is bad
- */
- retval = 0x3C;
- break;
- case 0x0810:
- /* Motorola base module extended feature register */
- retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
- break;
- case 0x0814:
- /* L2 invalidate: don't care */
- break;
- case 0x0818:
- /* Keylock */
- retval = 0x00;
- break;
- case 0x081C:
- /* system control register
- * 7 - 6 / 1 - 0: L2 cache enable
- */
- retval = sysctrl->syscontrol;
- break;
- case 0x0823:
- /* */
- retval = 0x03; /* no L2 cache */
- break;
- case 0x0850:
- /* I/O map type register */
- retval = sysctrl->contiguous_map;
- break;
- default:
- printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
- break;
- }
- trace_prep_io_800_readb(addr - PPC_IO_BASE, retval);
-
- return retval;
-}
-
-
#define NVRAM_SIZE 0x2000
static void fw_cfg_boot_set(void *opaque, const char *boot_device,
@@ -247,17 +78,6 @@ static void ppc_prep_reset(void *opaque)
cpu_reset(CPU(cpu));
}
-static const MemoryRegionPortio prep_portio_list[] = {
- /* System control ports */
- { 0x0092, 1, 1, .read = PREP_io_800_readb, .write = PREP_io_800_writeb, },
- { 0x0800, 0x52, 1,
- .read = PREP_io_800_readb, .write = PREP_io_800_writeb, },
- /* Special port to get debug messages from Open-Firmware */
- { 0x0F00, 4, 1, .write = PPC_debug_write, },
- PORTIO_END_OF_LIST(),
-};
-
-static PortioList prep_port_list;
/*****************************************************************************/
/* NVRAM helpers */
@@ -397,207 +217,6 @@ static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size,
return 0;
}
-/* PowerPC PREP hardware initialisation */
-static void ppc_prep_init(MachineState *machine)
-{
- ram_addr_t ram_size = machine->ram_size;
- const char *kernel_filename = machine->kernel_filename;
- const char *kernel_cmdline = machine->kernel_cmdline;
- const char *initrd_filename = machine->initrd_filename;
- const char *boot_device = machine->boot_order;
- MemoryRegion *sysmem = get_system_memory();
- PowerPCCPU *cpu = NULL;
- CPUPPCState *env = NULL;
- Nvram *m48t59;
-#if 0
- MemoryRegion *xcsr = g_new(MemoryRegion, 1);
-#endif
- int linux_boot, i, nb_nics1;
- MemoryRegion *ram = g_new(MemoryRegion, 1);
- uint32_t kernel_base, initrd_base;
- long kernel_size, initrd_size;
- DeviceState *dev;
- PCIHostState *pcihost;
- PCIBus *pci_bus;
- PCIDevice *pci;
- ISABus *isa_bus;
- ISADevice *isa;
- int ppc_boot_device;
- DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
-
- sysctrl = g_malloc0(sizeof(sysctrl_t));
-
- linux_boot = (kernel_filename != NULL);
-
- /* init CPUs */
- for (i = 0; i < machine->smp.cpus; i++) {
- cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
- env = &cpu->env;
-
- if (env->flags & POWERPC_FLAG_RTC_CLK) {
- /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
- cpu_ppc_tb_init(env, 7812500UL);
- } else {
- /* Set time-base frequency to 100 Mhz */
- cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
- }
- qemu_register_reset(ppc_prep_reset, cpu);
- }
-
- /* allocate RAM */
- memory_region_allocate_system_memory(ram, NULL, "ppc_prep.ram", ram_size);
- memory_region_add_subregion(sysmem, 0, ram);
-
- if (linux_boot) {
- kernel_base = KERNEL_LOAD_ADDR;
- /* now we can load the kernel */
- kernel_size = load_image_targphys(kernel_filename, kernel_base,
- ram_size - kernel_base);
- if (kernel_size < 0) {
- error_report("could not load kernel '%s'", kernel_filename);
- exit(1);
- }
- /* load initrd */
- if (initrd_filename) {
- initrd_base = INITRD_LOAD_ADDR;
- initrd_size = load_image_targphys(initrd_filename, initrd_base,
- ram_size - initrd_base);
- if (initrd_size < 0) {
- error_report("could not load initial ram disk '%s'",
- initrd_filename);
- exit(1);
- }
- } else {
- initrd_base = 0;
- initrd_size = 0;
- }
- ppc_boot_device = 'm';
- } else {
- kernel_base = 0;
- kernel_size = 0;
- initrd_base = 0;
- initrd_size = 0;
- ppc_boot_device = '\0';
- /* For now, OHW cannot boot from the network. */
- for (i = 0; boot_device[i] != '\0'; i++) {
- if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
- ppc_boot_device = boot_device[i];
- break;
- }
- }
- if (ppc_boot_device == '\0') {
- error_report("No valid boot device for Mac99 machine");
- exit(1);
- }
- }
-
- if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
- error_report("Only 6xx bus is supported on PREP machine");
- exit(1);
- }
-
- dev = qdev_create(NULL, "raven-pcihost");
- if (bios_name == NULL) {
- bios_name = BIOS_FILENAME;
- }
- qdev_prop_set_string(dev, "bios-name", bios_name);
- qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
- qdev_prop_set_bit(dev, "is-legacy-prep", true);
- pcihost = PCI_HOST_BRIDGE(dev);
- object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL);
- qdev_init_nofail(dev);
- pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
- if (pci_bus == NULL) {
- error_report("Couldn't create PCI host controller");
- exit(1);
- }
- sysctrl->contiguous_map_irq = qdev_get_gpio_in(dev, 0);
-
- /* PCI -> ISA bridge */
- pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378");
- cpu = POWERPC_CPU(first_cpu);
- qdev_connect_gpio_out(&pci->qdev, 0,
- cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
- sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev, 9));
- sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev, 11));
- sysbus_connect_irq(&pcihost->busdev, 2, qdev_get_gpio_in(&pci->qdev, 9));
- sysbus_connect_irq(&pcihost->busdev, 3, qdev_get_gpio_in(&pci->qdev, 11));
- isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci), "isa.0"));
-
- /* Super I/O (parallel + serial ports) */
- isa = isa_create(isa_bus, TYPE_PC87312_SUPERIO);
- dev = DEVICE(isa);
- qdev_prop_set_uint8(dev, "config", 13); /* fdc, ser0, ser1, par0 */
- qdev_init_nofail(dev);
-
- /* init basic PC hardware */
- pci_vga_init(pci_bus);
-
- nb_nics1 = nb_nics;
- if (nb_nics1 > NE2000_NB_MAX)
- nb_nics1 = NE2000_NB_MAX;
- for(i = 0; i < nb_nics1; i++) {
- if (nd_table[i].model == NULL) {
- nd_table[i].model = g_strdup("ne2k_isa");
- }
- if (strcmp(nd_table[i].model, "ne2k_isa") == 0) {
- isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i],
- &nd_table[i]);
- } else {
- pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
- }
- }
-
- ide_drive_get(hd, ARRAY_SIZE(hd));
- for(i = 0; i < MAX_IDE_BUS; i++) {
- isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i],
- hd[2 * i],
- hd[2 * i + 1]);
- }
-
- cpu = POWERPC_CPU(first_cpu);
- sysctrl->reset_irq = cpu->env.irq_inputs[PPC6xx_INPUT_HRESET];
-
- portio_list_init(&prep_port_list, NULL, prep_portio_list, sysctrl, "prep");
- portio_list_add(&prep_port_list, isa_address_space_io(isa), 0x0);
-
- /*
- * PowerPC control and status register group: unimplemented,
- * would be at address 0xFEFF0000.
- */
-
- if (machine_usb(machine)) {
- pci_create_simple(pci_bus, -1, "pci-ohci");
- }
-
- m48t59 = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 2000, 59);
- if (m48t59 == NULL)
- return;
- sysctrl->nvram = m48t59;
-
- /* Initialise NVRAM */
- PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size,
- ppc_boot_device,
- kernel_base, kernel_size,
- kernel_cmdline,
- initrd_base, initrd_size,
- /* XXX: need an option to load a NVRAM image */
- 0,
- graphic_width, graphic_height, graphic_depth);
-}
-
-static void prep_machine_init(MachineClass *mc)
-{
- mc->deprecation_reason = "use 40p machine type instead";
- mc->desc = "PowerPC PREP platform";
- mc->init = ppc_prep_init;
- mc->block_default_type = IF_IDE;
- mc->max_cpus = MAX_CPUS;
- mc->default_boot_order = "cad";
- mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("602");
- mc->default_display = "std";
-}
-
static int prep_set_cmos_checksum(DeviceState *dev, void *opaque)
{
uint16_t checksum = *(uint16_t *)opaque;
@@ -821,4 +440,3 @@ static void ibm_40p_machine_init(MachineClass *mc)
}
DEFINE_MACHINE("40p", ibm_40p_machine_init)
-DEFINE_MACHINE("prep", prep_machine_init)
diff --git a/include/hw/ppc/ppc.h b/include/hw/ppc/ppc.h
index 4bdcb8bacd..94b28f77f6 100644
--- a/include/hw/ppc/ppc.h
+++ b/include/hw/ppc/ppc.h
@@ -67,7 +67,6 @@ clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq,
void ppc40x_core_reset(PowerPCCPU *cpu);
void ppc40x_chip_reset(PowerPCCPU *cpu);
void ppc40x_system_reset(PowerPCCPU *cpu);
-void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
#if defined(CONFIG_USER_ONLY)
static inline void ppc40x_irq_init(PowerPCCPU *cpu) {}
diff --git a/pc-bios/README b/pc-bios/README
index 830645c51f..062c11a9eb 100644
--- a/pc-bios/README
+++ b/pc-bios/README
@@ -4,9 +4,6 @@
- The VGA BIOS and the Cirrus VGA BIOS come from the LGPL VGA bios
project (http://www.nongnu.org/vgabios/).
-- The PowerPC Open Hack'Ware Open Firmware Compatible BIOS is
- available at https://repo.or.cz/openhackware.git.
-
- OpenBIOS (http://www.openbios.org/) is a free (GPL v2) portable
firmware implementation. The goal is to implement a 100% IEEE
1275-1994 (referred to as Open Firmware) compliant firmware.
diff --git a/pc-bios/ppc_rom.bin b/pc-bios/ppc_rom.bin
deleted file mode 100644
index 174a24744b73fb2824f9b1e7c0078f4499e1e724..0000000000000000000000000000000000000000
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z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
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zNxMAkyQiw$%yV=)PbRl#X_n(^bDwtDv_7lS4CCtYEA{Jl>hp}ho9<%U-L|g#9A9Lw
O-*vaY{|j7>>w`a^<P%E(
diff --git a/qemu-deprecated.texi b/qemu-deprecated.texi
index 4b4b7425ac..66d2b22a94 100644
--- a/qemu-deprecated.texi
+++ b/qemu-deprecated.texi
@@ -271,12 +271,6 @@ The 'scsi-disk' device is deprecated. Users should use 'scsi-hd' or
These machine types are very old and likely can not be used for live migration
from old QEMU versions anymore. A newer machine type should be used instead.
-@subsection prep (PowerPC) (since 3.1)
-
-This machine type uses an unmaintained firmware, broken in lots of ways,
-and unable to start post-2004 operating systems. 40p machine type should be
-used instead.
-
@subsection spike_v1.9.1 and spike_v1.10 (since 4.1)
The version specific Spike machines have been deprecated in favour of the
diff --git a/qemu-doc.texi b/qemu-doc.texi
index 3ddf5c0a68..f8037f12ef 100644
--- a/qemu-doc.texi
+++ b/qemu-doc.texi
@@ -1763,7 +1763,7 @@ differences are mentioned in the following sections.
@section PowerPC System emulator
@cindex system emulation (PowerPC)
-Use the executable @file{qemu-system-ppc} to simulate a complete PREP
+Use the executable @file{qemu-system-ppc} to simulate a complete 40P (PREP)
or PowerMac PowerPC system.
QEMU emulates the following PowerMac peripherals:
@@ -1783,7 +1783,7 @@ Non Volatile RAM
VIA-CUDA with ADB keyboard and mouse.
@end itemize
-QEMU emulates the following PREP peripherals:
+QEMU emulates the following 40P (PREP) peripherals:
@itemize @minus
@item
@@ -1795,7 +1795,7 @@ PCI VGA compatible card with VESA Bochs Extensions
@item
Floppy disk
@item
-NE2000 network adapters
+PCnet network adapters
@item
Serial port
@item
@@ -1804,12 +1804,9 @@ PREP Non Volatile RAM
PC compatible keyboard and mouse.
@end itemize
-QEMU uses the Open Hack'Ware Open Firmware Compatible BIOS available at
-@url{http://perso.magic.fr/l_indien/OpenHackWare/index.htm}.
-
Since version 0.9.1, QEMU uses OpenBIOS @url{https://www.openbios.org/}
-for the g3beige and mac99 PowerMac machines. OpenBIOS is a free (GPL
-v2) portable firmware implementation. The goal is to implement a 100%
+for the g3beige and mac99 PowerMac and the 40p machines. OpenBIOS is a free
+(GPL v2) portable firmware implementation. The goal is to implement a 100%
IEEE 1275-1994 (referred to as Open Firmware) compliant firmware.
@c man begin OPTIONS
@@ -1832,8 +1829,6 @@ qemu-system-ppc -prom-env 'auto-boot?=false' \
-prom-env 'boot-args=conf=hd:2,\yaboot.conf'
@end example
-These variables are not used by Open Hack'Ware.
-
@end table
@c man end
diff --git a/roms/openhackware b/roms/openhackware
deleted file mode 160000
index c559da7c8e..0000000000
--- a/roms/openhackware
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit c559da7c8eec5e45ef1f67978827af6f0b9546f5
diff --git a/tests/boot-order-test.c b/tests/boot-order-test.c
index a725bce729..4a6218a516 100644
--- a/tests/boot-order-test.c
+++ b/tests/boot-order-test.c
@@ -108,30 +108,6 @@ static void test_pc_boot_order(void)
test_boot_orders(NULL, read_boot_order_pc, test_cases_pc);
}
-static uint8_t read_m48t59(QTestState *qts, uint64_t addr, uint16_t reg)
-{
- qtest_writeb(qts, addr, reg & 0xff);
- qtest_writeb(qts, addr + 1, reg >> 8);
- return qtest_readb(qts, addr + 3);
-}
-
-static uint64_t read_boot_order_prep(QTestState *qts)
-{
- return read_m48t59(qts, 0x80000000 + 0x74, 0x34);
-}
-
-static const boot_order_test test_cases_prep[] = {
- { "", 'c', 'c' },
- { "-boot c", 'c', 'c' },
- { "-boot d", 'd', 'd' },
- {}
-};
-
-static void test_prep_boot_order(void)
-{
- test_boot_orders("prep", read_boot_order_prep, test_cases_prep);
-}
-
static uint64_t read_boot_order_pmac(QTestState *qts)
{
QFWCFG *fw_cfg = mm_fw_cfg_init(qts, 0xf0000510);
@@ -190,7 +166,6 @@ int main(int argc, char *argv[])
if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) {
qtest_add_func("boot-order/pc", test_pc_boot_order);
} else if (strcmp(arch, "ppc") == 0 || strcmp(arch, "ppc64") == 0) {
- qtest_add_func("boot-order/prep", test_prep_boot_order);
qtest_add_func("boot-order/pmac_oldworld",
test_pmac_oldworld_boot_order);
qtest_add_func("boot-order/pmac_newworld",
diff --git a/tests/cdrom-test.c b/tests/cdrom-test.c
index 34e9974634..006044f48a 100644
--- a/tests/cdrom-test.c
+++ b/tests/cdrom-test.c
@@ -189,7 +189,7 @@ int main(int argc, char **argv)
add_s390x_tests();
} else if (g_str_equal(arch, "ppc64")) {
const char *ppcmachines[] = {
- "pseries", "mac99", "g3beige", "40p", "prep", NULL
+ "pseries", "mac99", "g3beige", "40p", NULL
};
add_cdrom_param_tests(ppcmachines);
} else if (g_str_equal(arch, "sparc")) {
diff --git a/tests/endianness-test.c b/tests/endianness-test.c
index 58527952a5..2798802c63 100644
--- a/tests/endianness-test.c
+++ b/tests/endianness-test.c
@@ -35,7 +35,7 @@ static const TestCase test_cases[] = {
{ "mips64", "malta", 0x10000000, .bswap = true },
{ "mips64el", "fulong2e", 0x1fd00000 },
{ "ppc", "g3beige", 0xfe000000, .bswap = true, .superio = "i82378" },
- { "ppc", "prep", 0x80000000, .bswap = true },
+ { "ppc", "40p", 0x80000000, .bswap = true },
{ "ppc", "bamboo", 0xe8000000, .bswap = true, .superio = "i82378" },
{ "ppc64", "mac99", 0xf2000000, .bswap = true, .superio = "i82378" },
{ "ppc64", "pseries", (1ULL << 45), .bswap = true, .superio = "i82378" },
--
2.23.0
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH] hw/ppc/prep: Remove the deprecated "prep" machine and the OpenHackware BIOS
2019-12-03 7:29 [PATCH] hw/ppc/prep: Remove the deprecated "prep" machine and the OpenHackware BIOS Thomas Huth
@ 2019-12-03 7:45 ` Philippe Mathieu-Daudé
2019-12-03 8:25 ` Thomas Huth
2020-01-07 9:22 ` Thomas Huth
1 sibling, 1 reply; 12+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-12-03 7:45 UTC (permalink / raw)
To: Thomas Huth, qemu-devel, David Gibson, Hervé Poussineau
Cc: Laurent Vivier
On 12/3/19 8:29 AM, Thomas Huth wrote:
> It's been deprecated since QEMU v3.1. The 40p machine should be
> used nowadays instead.
>
> Signed-off-by: Thomas Huth <thuth@redhat.com>
> ---
> .gitmodules | 3 -
> MAINTAINERS | 1 -
> Makefile | 2 +-
> docs/interop/firmware.json | 3 +-
> hw/ppc/ppc.c | 18 --
> hw/ppc/prep.c | 384 +------------------------------------
> include/hw/ppc/ppc.h | 1 -
> pc-bios/README | 3 -
> pc-bios/ppc_rom.bin | Bin 1048576 -> 0 bytes
> qemu-deprecated.texi | 6 -
> qemu-doc.texi | 15 +-
> roms/openhackware | 1 -
> tests/boot-order-test.c | 25 ---
> tests/cdrom-test.c | 2 +-
> tests/endianness-test.c | 2 +-
> 15 files changed, 10 insertions(+), 456 deletions(-)
> delete mode 100644 pc-bios/ppc_rom.bin
> delete mode 160000 roms/openhackware
[...]
> diff --git a/tests/boot-order-test.c b/tests/boot-order-test.c
> index a725bce729..4a6218a516 100644
> --- a/tests/boot-order-test.c
> +++ b/tests/boot-order-test.c
> @@ -108,30 +108,6 @@ static void test_pc_boot_order(void)
> test_boot_orders(NULL, read_boot_order_pc, test_cases_pc);
> }
>
> -static uint8_t read_m48t59(QTestState *qts, uint64_t addr, uint16_t reg)
> -{
> - qtest_writeb(qts, addr, reg & 0xff);
> - qtest_writeb(qts, addr + 1, reg >> 8);
> - return qtest_readb(qts, addr + 3);
> -}
> -
> -static uint64_t read_boot_order_prep(QTestState *qts)
> -{
> - return read_m48t59(qts, 0x80000000 + 0x74, 0x34);
I'd rather keep this generic mmio-mapped ISA test.
Maybe run it with the 40p machine?
Maybe we can rename this as read_boot_order_mm, and the previous
read_boot_order_pc as read_boot_order_io.
Except this comment, thanks for this cleaning.
Ideally keeping read_boot_order_io test:
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> -}
> -
> -static const boot_order_test test_cases_prep[] = {
> - { "", 'c', 'c' },
> - { "-boot c", 'c', 'c' },
> - { "-boot d", 'd', 'd' },
> - {}
> -};
> -
> -static void test_prep_boot_order(void)
> -{
> - test_boot_orders("prep", read_boot_order_prep, test_cases_prep);
> -}
> -
> static uint64_t read_boot_order_pmac(QTestState *qts)
> {
> QFWCFG *fw_cfg = mm_fw_cfg_init(qts, 0xf0000510);
> @@ -190,7 +166,6 @@ int main(int argc, char *argv[])
> if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) {
> qtest_add_func("boot-order/pc", test_pc_boot_order);
> } else if (strcmp(arch, "ppc") == 0 || strcmp(arch, "ppc64") == 0) {
> - qtest_add_func("boot-order/prep", test_prep_boot_order);
> qtest_add_func("boot-order/pmac_oldworld",
> test_pmac_oldworld_boot_order);
> qtest_add_func("boot-order/pmac_newworld",
> diff --git a/tests/cdrom-test.c b/tests/cdrom-test.c
> index 34e9974634..006044f48a 100644
> --- a/tests/cdrom-test.c
> +++ b/tests/cdrom-test.c
> @@ -189,7 +189,7 @@ int main(int argc, char **argv)
> add_s390x_tests();
> } else if (g_str_equal(arch, "ppc64")) {
> const char *ppcmachines[] = {
> - "pseries", "mac99", "g3beige", "40p", "prep", NULL
> + "pseries", "mac99", "g3beige", "40p", NULL
> };
> add_cdrom_param_tests(ppcmachines);
> } else if (g_str_equal(arch, "sparc")) {
> diff --git a/tests/endianness-test.c b/tests/endianness-test.c
> index 58527952a5..2798802c63 100644
> --- a/tests/endianness-test.c
> +++ b/tests/endianness-test.c
> @@ -35,7 +35,7 @@ static const TestCase test_cases[] = {
> { "mips64", "malta", 0x10000000, .bswap = true },
> { "mips64el", "fulong2e", 0x1fd00000 },
> { "ppc", "g3beige", 0xfe000000, .bswap = true, .superio = "i82378" },
> - { "ppc", "prep", 0x80000000, .bswap = true },
> + { "ppc", "40p", 0x80000000, .bswap = true },
> { "ppc", "bamboo", 0xe8000000, .bswap = true, .superio = "i82378" },
> { "ppc64", "mac99", 0xf2000000, .bswap = true, .superio = "i82378" },
> { "ppc64", "pseries", (1ULL << 45), .bswap = true, .superio = "i82378" },
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] hw/ppc/prep: Remove the deprecated "prep" machine and the OpenHackware BIOS
2019-12-03 7:45 ` Philippe Mathieu-Daudé
@ 2019-12-03 8:25 ` Thomas Huth
2019-12-03 8:51 ` Philippe Mathieu-Daudé
2019-12-03 22:36 ` Mark Cave-Ayland
0 siblings, 2 replies; 12+ messages in thread
From: Thomas Huth @ 2019-12-03 8:25 UTC (permalink / raw)
To: Philippe Mathieu-Daudé,
qemu-devel, David Gibson, Hervé Poussineau
Cc: Laurent Vivier
On 03/12/2019 08.45, Philippe Mathieu-Daudé wrote:
> On 12/3/19 8:29 AM, Thomas Huth wrote:
>> It's been deprecated since QEMU v3.1. The 40p machine should be
>> used nowadays instead.
>>
>> Signed-off-by: Thomas Huth <thuth@redhat.com>
>> ---
>> .gitmodules | 3 -
>> MAINTAINERS | 1 -
>> Makefile | 2 +-
>> docs/interop/firmware.json | 3 +-
>> hw/ppc/ppc.c | 18 --
>> hw/ppc/prep.c | 384 +------------------------------------
>> include/hw/ppc/ppc.h | 1 -
>> pc-bios/README | 3 -
>> pc-bios/ppc_rom.bin | Bin 1048576 -> 0 bytes
>> qemu-deprecated.texi | 6 -
>> qemu-doc.texi | 15 +-
>> roms/openhackware | 1 -
>> tests/boot-order-test.c | 25 ---
>> tests/cdrom-test.c | 2 +-
>> tests/endianness-test.c | 2 +-
>> 15 files changed, 10 insertions(+), 456 deletions(-)
>> delete mode 100644 pc-bios/ppc_rom.bin
>> delete mode 160000 roms/openhackware
> [...]
>> diff --git a/tests/boot-order-test.c b/tests/boot-order-test.c
>> index a725bce729..4a6218a516 100644
>> --- a/tests/boot-order-test.c
>> +++ b/tests/boot-order-test.c
>> @@ -108,30 +108,6 @@ static void test_pc_boot_order(void)
>> test_boot_orders(NULL, read_boot_order_pc, test_cases_pc);
>> }
>> -static uint8_t read_m48t59(QTestState *qts, uint64_t addr, uint16_t
>> reg)
>> -{
>> - qtest_writeb(qts, addr, reg & 0xff);
>> - qtest_writeb(qts, addr + 1, reg >> 8);
>> - return qtest_readb(qts, addr + 3);
>> -}
>> -
>> -static uint64_t read_boot_order_prep(QTestState *qts)
>> -{
>> - return read_m48t59(qts, 0x80000000 + 0x74, 0x34);
>
> I'd rather keep this generic mmio-mapped ISA test.
> Maybe run it with the 40p machine?
I don't think that this is possible in an easy way here. On the prep
machine, the ISA bus is on a hard-coded MMIO address. On the 40p
machine, the ISA bus is behind a PCI-to-ISA bridge, thus the PCI part
needs to be set up first.
> Maybe we can rename this as read_boot_order_mm, and the previous
> read_boot_order_pc as read_boot_order_io.
I don't think it makes much sense. This was completely specific to the
"prep" machine, even the "40p" machine seems to prefer fw_cfg nowadays.
So let's simply remove this old stuff.
Thomas
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] hw/ppc/prep: Remove the deprecated "prep" machine and the OpenHackware BIOS
2019-12-03 8:25 ` Thomas Huth
@ 2019-12-03 8:51 ` Philippe Mathieu-Daudé
2019-12-03 9:15 ` Thomas Huth
2019-12-03 22:36 ` Mark Cave-Ayland
1 sibling, 1 reply; 12+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-12-03 8:51 UTC (permalink / raw)
To: Thomas Huth, qemu-devel, David Gibson, Hervé Poussineau
Cc: Laurent Vivier
On 12/3/19 9:25 AM, Thomas Huth wrote:
> On 03/12/2019 08.45, Philippe Mathieu-Daudé wrote:
>> On 12/3/19 8:29 AM, Thomas Huth wrote:
>>> It's been deprecated since QEMU v3.1. The 40p machine should be
>>> used nowadays instead.
>>>
>>> Signed-off-by: Thomas Huth <thuth@redhat.com>
>>> ---
>>> .gitmodules | 3 -
>>> MAINTAINERS | 1 -
>>> Makefile | 2 +-
>>> docs/interop/firmware.json | 3 +-
>>> hw/ppc/ppc.c | 18 --
>>> hw/ppc/prep.c | 384 +------------------------------------
>>> include/hw/ppc/ppc.h | 1 -
>>> pc-bios/README | 3 -
>>> pc-bios/ppc_rom.bin | Bin 1048576 -> 0 bytes
>>> qemu-deprecated.texi | 6 -
>>> qemu-doc.texi | 15 +-
>>> roms/openhackware | 1 -
>>> tests/boot-order-test.c | 25 ---
>>> tests/cdrom-test.c | 2 +-
>>> tests/endianness-test.c | 2 +-
>>> 15 files changed, 10 insertions(+), 456 deletions(-)
>>> delete mode 100644 pc-bios/ppc_rom.bin
>>> delete mode 160000 roms/openhackware
>> [...]
>>> diff --git a/tests/boot-order-test.c b/tests/boot-order-test.c
>>> index a725bce729..4a6218a516 100644
>>> --- a/tests/boot-order-test.c
>>> +++ b/tests/boot-order-test.c
>>> @@ -108,30 +108,6 @@ static void test_pc_boot_order(void)
>>> test_boot_orders(NULL, read_boot_order_pc, test_cases_pc);
>>> }
>>> -static uint8_t read_m48t59(QTestState *qts, uint64_t addr, uint16_t
>>> reg)
>>> -{
>>> - qtest_writeb(qts, addr, reg & 0xff);
>>> - qtest_writeb(qts, addr + 1, reg >> 8);
>>> - return qtest_readb(qts, addr + 3);
>>> -}
>>> -
>>> -static uint64_t read_boot_order_prep(QTestState *qts)
>>> -{
>>> - return read_m48t59(qts, 0x80000000 + 0x74, 0x34);
>>
>> I'd rather keep this generic mmio-mapped ISA test.
>> Maybe run it with the 40p machine?
>
> I don't think that this is possible in an easy way here. On the prep
> machine, the ISA bus is on a hard-coded MMIO address. On the 40p
> machine, the ISA bus is behind a PCI-to-ISA bridge, thus the PCI part
> needs to be set up first.
The why ...
>> Maybe we can rename this as read_boot_order_mm, and the previous
>> read_boot_order_pc as read_boot_order_io.
>
> I don't think it makes much sense. This was completely specific to the
> "prep" machine, even the "40p" machine seems to prefer fw_cfg nowadays.
> So let's simply remove this old stuff.
>
>> diff --git a/tests/endianness-test.c b/tests/endianness-test.c
>> index 58527952a5..2798802c63 100644
>> --- a/tests/endianness-test.c
>> +++ b/tests/endianness-test.c
>> @@ -35,7 +35,7 @@ static const TestCase test_cases[] = {
>> { "mips64", "malta", 0x10000000, .bswap = true },
>> { "mips64el", "fulong2e", 0x1fd00000 },
>> { "ppc", "g3beige", 0xfe000000, .bswap = true, .superio =
>> "i82378" },
>> - { "ppc", "prep", 0x80000000, .bswap = true },
>> + { "ppc", "40p", 0x80000000, .bswap = true },
... here you access the Super I/O behind the PCI bridge via MMIO?
>> { "ppc", "bamboo", 0xe8000000, .bswap = true, .superio =
>> "i82378" },
>> { "ppc64", "mac99", 0xf2000000, .bswap = true, .superio =
>> "i82378" },
>> { "ppc64", "pseries", (1ULL << 45), .bswap = true, .superio =
>> "i82378" },
>>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] hw/ppc/prep: Remove the deprecated "prep" machine and the OpenHackware BIOS
2019-12-03 8:51 ` Philippe Mathieu-Daudé
@ 2019-12-03 9:15 ` Thomas Huth
2019-12-03 9:21 ` Philippe Mathieu-Daudé
2019-12-03 13:04 ` Paolo Bonzini
0 siblings, 2 replies; 12+ messages in thread
From: Thomas Huth @ 2019-12-03 9:15 UTC (permalink / raw)
To: Philippe Mathieu-Daudé,
qemu-devel, David Gibson, Hervé Poussineau
Cc: Laurent Vivier
On 03/12/2019 09.51, Philippe Mathieu-Daudé wrote:
> On 12/3/19 9:25 AM, Thomas Huth wrote:
>> On 03/12/2019 08.45, Philippe Mathieu-Daudé wrote:
>>> On 12/3/19 8:29 AM, Thomas Huth wrote:
>>>> It's been deprecated since QEMU v3.1. The 40p machine should be
>>>> used nowadays instead.
>>>>
>>>> Signed-off-by: Thomas Huth <thuth@redhat.com>
>>>> ---
>>>> .gitmodules | 3 -
>>>> MAINTAINERS | 1 -
>>>> Makefile | 2 +-
>>>> docs/interop/firmware.json | 3 +-
>>>> hw/ppc/ppc.c | 18 --
>>>> hw/ppc/prep.c | 384
>>>> +------------------------------------
>>>> include/hw/ppc/ppc.h | 1 -
>>>> pc-bios/README | 3 -
>>>> pc-bios/ppc_rom.bin | Bin 1048576 -> 0 bytes
>>>> qemu-deprecated.texi | 6 -
>>>> qemu-doc.texi | 15 +-
>>>> roms/openhackware | 1 -
>>>> tests/boot-order-test.c | 25 ---
>>>> tests/cdrom-test.c | 2 +-
>>>> tests/endianness-test.c | 2 +-
>>>> 15 files changed, 10 insertions(+), 456 deletions(-)
>>>> delete mode 100644 pc-bios/ppc_rom.bin
>>>> delete mode 160000 roms/openhackware
>>> [...]
>>>> diff --git a/tests/boot-order-test.c b/tests/boot-order-test.c
>>>> index a725bce729..4a6218a516 100644
>>>> --- a/tests/boot-order-test.c
>>>> +++ b/tests/boot-order-test.c
>>>> @@ -108,30 +108,6 @@ static void test_pc_boot_order(void)
>>>> test_boot_orders(NULL, read_boot_order_pc, test_cases_pc);
>>>> }
>>>> -static uint8_t read_m48t59(QTestState *qts, uint64_t addr, uint16_t
>>>> reg)
>>>> -{
>>>> - qtest_writeb(qts, addr, reg & 0xff);
>>>> - qtest_writeb(qts, addr + 1, reg >> 8);
>>>> - return qtest_readb(qts, addr + 3);
>>>> -}
>>>> -
>>>> -static uint64_t read_boot_order_prep(QTestState *qts)
>>>> -{
>>>> - return read_m48t59(qts, 0x80000000 + 0x74, 0x34);
>>>
>>> I'd rather keep this generic mmio-mapped ISA test.
>>> Maybe run it with the 40p machine?
>>
>> I don't think that this is possible in an easy way here. On the prep
>> machine, the ISA bus is on a hard-coded MMIO address. On the 40p
>> machine, the ISA bus is behind a PCI-to-ISA bridge, thus the PCI part
>> needs to be set up first.
>
> The why ...
If you don't believe me, why don't you simply try to adapt the test on
your own to use the 40p machine instead?
>>> Maybe we can rename this as read_boot_order_mm, and the previous
>>> read_boot_order_pc as read_boot_order_io.
>>
>> I don't think it makes much sense. This was completely specific to the
>> "prep" machine, even the "40p" machine seems to prefer fw_cfg nowadays.
>> So let's simply remove this old stuff.
>>
>>> diff --git a/tests/endianness-test.c b/tests/endianness-test.c
>>> index 58527952a5..2798802c63 100644
>>> --- a/tests/endianness-test.c
>>> +++ b/tests/endianness-test.c
>>> @@ -35,7 +35,7 @@ static const TestCase test_cases[] = {
>>> { "mips64", "malta", 0x10000000, .bswap = true },
>>> { "mips64el", "fulong2e", 0x1fd00000 },
>>> { "ppc", "g3beige", 0xfe000000, .bswap = true, .superio =
>>> "i82378" },
>>> - { "ppc", "prep", 0x80000000, .bswap = true },
>>> + { "ppc", "40p", 0x80000000, .bswap = true },
>
> ... here you access the Super I/O behind the PCI bridge via MMIO?
The difference is that this is an *arbitrary* address in I/O space
there. It's not an address of a certain PCI device like the m48t59
behind a PCI-bridge. As long as it's possible to write and read from
this address, the test is working. Both, the "prep" and the "40p"
machine have the "raven-pcihost" device at this address, so in this case
the switch from "40p" to "prep" was easily possible.
Thomas
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] hw/ppc/prep: Remove the deprecated "prep" machine and the OpenHackware BIOS
2019-12-03 9:15 ` Thomas Huth
@ 2019-12-03 9:21 ` Philippe Mathieu-Daudé
2019-12-03 13:04 ` Paolo Bonzini
1 sibling, 0 replies; 12+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-12-03 9:21 UTC (permalink / raw)
To: Thomas Huth, qemu-devel, David Gibson, Hervé Poussineau
Cc: Laurent Vivier
On 12/3/19 10:15 AM, Thomas Huth wrote:
> On 03/12/2019 09.51, Philippe Mathieu-Daudé wrote:
>> On 12/3/19 9:25 AM, Thomas Huth wrote:
>>> On 03/12/2019 08.45, Philippe Mathieu-Daudé wrote:
>>>> On 12/3/19 8:29 AM, Thomas Huth wrote:
>>>>> It's been deprecated since QEMU v3.1. The 40p machine should be
>>>>> used nowadays instead.
>>>>>
>>>>> Signed-off-by: Thomas Huth <thuth@redhat.com>
>>>>> ---
>>>>> .gitmodules | 3 -
>>>>> MAINTAINERS | 1 -
>>>>> Makefile | 2 +-
>>>>> docs/interop/firmware.json | 3 +-
>>>>> hw/ppc/ppc.c | 18 --
>>>>> hw/ppc/prep.c | 384
>>>>> +------------------------------------
>>>>> include/hw/ppc/ppc.h | 1 -
>>>>> pc-bios/README | 3 -
>>>>> pc-bios/ppc_rom.bin | Bin 1048576 -> 0 bytes
>>>>> qemu-deprecated.texi | 6 -
>>>>> qemu-doc.texi | 15 +-
>>>>> roms/openhackware | 1 -
>>>>> tests/boot-order-test.c | 25 ---
>>>>> tests/cdrom-test.c | 2 +-
>>>>> tests/endianness-test.c | 2 +-
>>>>> 15 files changed, 10 insertions(+), 456 deletions(-)
>>>>> delete mode 100644 pc-bios/ppc_rom.bin
>>>>> delete mode 160000 roms/openhackware
>>>> [...]
>>>>> diff --git a/tests/boot-order-test.c b/tests/boot-order-test.c
>>>>> index a725bce729..4a6218a516 100644
>>>>> --- a/tests/boot-order-test.c
>>>>> +++ b/tests/boot-order-test.c
>>>>> @@ -108,30 +108,6 @@ static void test_pc_boot_order(void)
>>>>> test_boot_orders(NULL, read_boot_order_pc, test_cases_pc);
>>>>> }
>>>>> -static uint8_t read_m48t59(QTestState *qts, uint64_t addr, uint16_t
>>>>> reg)
>>>>> -{
>>>>> - qtest_writeb(qts, addr, reg & 0xff);
>>>>> - qtest_writeb(qts, addr + 1, reg >> 8);
>>>>> - return qtest_readb(qts, addr + 3);
>>>>> -}
>>>>> -
>>>>> -static uint64_t read_boot_order_prep(QTestState *qts)
>>>>> -{
>>>>> - return read_m48t59(qts, 0x80000000 + 0x74, 0x34);
>>>>
>>>> I'd rather keep this generic mmio-mapped ISA test.
>>>> Maybe run it with the 40p machine?
>>>
>>> I don't think that this is possible in an easy way here. On the prep
>>> machine, the ISA bus is on a hard-coded MMIO address. On the 40p
>>> machine, the ISA bus is behind a PCI-to-ISA bridge, thus the PCI part
>>> needs to be set up first.
>>
>> The why ...
>
I meant "TheN why". The "..." were to continue the review comment below
the endianness-test.c diff.
> If you don't believe me, why don't you simply try to adapt the test on
> your own to use the 40p machine instead?
I didn't meant to be rude, I'm sorry if you misunderstood me.
>>>> Maybe we can rename this as read_boot_order_mm, and the previous
>>>> read_boot_order_pc as read_boot_order_io.
>>>
>>> I don't think it makes much sense. This was completely specific to the
>>> "prep" machine, even the "40p" machine seems to prefer fw_cfg nowadays.
>>> So let's simply remove this old stuff.
>>>
>>>> diff --git a/tests/endianness-test.c b/tests/endianness-test.c
>>>> index 58527952a5..2798802c63 100644
>>>> --- a/tests/endianness-test.c
>>>> +++ b/tests/endianness-test.c
>>>> @@ -35,7 +35,7 @@ static const TestCase test_cases[] = {
>>>> { "mips64", "malta", 0x10000000, .bswap = true },
>>>> { "mips64el", "fulong2e", 0x1fd00000 },
>>>> { "ppc", "g3beige", 0xfe000000, .bswap = true, .superio =
>>>> "i82378" },
>>>> - { "ppc", "prep", 0x80000000, .bswap = true },
>>>> + { "ppc", "40p", 0x80000000, .bswap = true },
>>
>> ... here you access the Super I/O behind the PCI bridge via MMIO?
>
> The difference is that this is an *arbitrary* address in I/O space
> there. It's not an address of a certain PCI device like the m48t59
> behind a PCI-bridge. As long as it's possible to write and read from
> this address, the test is working. Both, the "prep" and the "40p"
> machine have the "raven-pcihost" device at this address, so in this case
> the switch from "40p" to "prep" was easily possible.
Now I better understand what this test does, thanks.
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] hw/ppc/prep: Remove the deprecated "prep" machine and the OpenHackware BIOS
2019-12-03 9:15 ` Thomas Huth
2019-12-03 9:21 ` Philippe Mathieu-Daudé
@ 2019-12-03 13:04 ` Paolo Bonzini
2019-12-03 13:16 ` Thomas Huth
1 sibling, 1 reply; 12+ messages in thread
From: Paolo Bonzini @ 2019-12-03 13:04 UTC (permalink / raw)
To: Thomas Huth, Philippe Mathieu-Daudé,
qemu-devel, David Gibson, Hervé Poussineau
Cc: Laurent Vivier
On 03/12/19 10:15, Thomas Huth wrote:
>>>> Maybe we can rename this as read_boot_order_mm, and the previous
>>>> read_boot_order_pc as read_boot_order_io.
>>>
>>> I don't think it makes much sense. This was completely specific to the
>>> "prep" machine, even the "40p" machine seems to prefer fw_cfg nowadays.
>>> So let's simply remove this old stuff.
>>>
>>>> diff --git a/tests/endianness-test.c b/tests/endianness-test.c
>>>> index 58527952a5..2798802c63 100644
>>>> --- a/tests/endianness-test.c
>>>> +++ b/tests/endianness-test.c
>>>> @@ -35,7 +35,7 @@ static const TestCase test_cases[] = {
>>>> { "mips64", "malta", 0x10000000, .bswap = true },
>>>> { "mips64el", "fulong2e", 0x1fd00000 },
>>>> { "ppc", "g3beige", 0xfe000000, .bswap = true, .superio =
>>>> "i82378" },
>>>> - { "ppc", "prep", 0x80000000, .bswap = true },
>>>> + { "ppc", "40p", 0x80000000, .bswap = true },
>>
>> ... here you access the Super I/O behind the PCI bridge via MMIO?
>
> The difference is that this is an *arbitrary* address in I/O space
> there.
No, it's the base address of the ISA space, to which the tests add the
address of the pc-testdev device. It's not any different from the
0x80000000 in boot-order-test.
That said, I think it's a sensible objection that boot order doesn't
come from m48t59 on 40p (does it not?). The m48t59-test could also be
adjusted to test the 40p... the right way to do it would be to have an
ISA bridge driver in qgraph, but that's a topic for a separate series.
Thanks,
Paolo
> It's not an address of a certain PCI device like the m48t59
> behind a PCI-bridge. As long as it's possible to write and read from
> this address, the test is working. Both, the "prep" and the "40p"
> machine have the "raven-pcihost" device at this address, so in this case
> the switch from "40p" to "prep" was easily possible.
>
> Thomas
>
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] hw/ppc/prep: Remove the deprecated "prep" machine and the OpenHackware BIOS
2019-12-03 13:04 ` Paolo Bonzini
@ 2019-12-03 13:16 ` Thomas Huth
2019-12-03 13:39 ` Paolo Bonzini
0 siblings, 1 reply; 12+ messages in thread
From: Thomas Huth @ 2019-12-03 13:16 UTC (permalink / raw)
To: Paolo Bonzini, Philippe Mathieu-Daudé,
qemu-devel, David Gibson, Hervé Poussineau
Cc: Laurent Vivier
On 03/12/2019 14.04, Paolo Bonzini wrote:
> On 03/12/19 10:15, Thomas Huth wrote:
>>>>> Maybe we can rename this as read_boot_order_mm, and the previous
>>>>> read_boot_order_pc as read_boot_order_io.
>>>>
>>>> I don't think it makes much sense. This was completely specific to the
>>>> "prep" machine, even the "40p" machine seems to prefer fw_cfg nowadays.
>>>> So let's simply remove this old stuff.
>>>>
>>>>> diff --git a/tests/endianness-test.c b/tests/endianness-test.c
>>>>> index 58527952a5..2798802c63 100644
>>>>> --- a/tests/endianness-test.c
>>>>> +++ b/tests/endianness-test.c
>>>>> @@ -35,7 +35,7 @@ static const TestCase test_cases[] = {
>>>>> { "mips64", "malta", 0x10000000, .bswap = true },
>>>>> { "mips64el", "fulong2e", 0x1fd00000 },
>>>>> { "ppc", "g3beige", 0xfe000000, .bswap = true, .superio =
>>>>> "i82378" },
>>>>> - { "ppc", "prep", 0x80000000, .bswap = true },
>>>>> + { "ppc", "40p", 0x80000000, .bswap = true },
>>>
>>> ... here you access the Super I/O behind the PCI bridge via MMIO?
>>
>> The difference is that this is an *arbitrary* address in I/O space
>> there.
>
> No, it's the base address of the ISA space, to which the tests add the
> address of the pc-testdev device. It's not any different from the
> 0x80000000 in boot-order-test.
Hmm, interesting. Why is it not necessary to set up the BARs of the
PCI-to-ISA bridge in this case?
> That said, I think it's a sensible objection that boot order doesn't
> come from m48t59 on 40p (does it not?).
Right. I'm also not an expert here, but I think the OpenBIOS on 40p
rather uses fw_cfg instead.
Thomas
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] hw/ppc/prep: Remove the deprecated "prep" machine and the OpenHackware BIOS
2019-12-03 13:16 ` Thomas Huth
@ 2019-12-03 13:39 ` Paolo Bonzini
0 siblings, 0 replies; 12+ messages in thread
From: Paolo Bonzini @ 2019-12-03 13:39 UTC (permalink / raw)
To: Thomas Huth, Philippe Mathieu-Daudé,
qemu-devel, David Gibson, Hervé Poussineau
Cc: Laurent Vivier
On 03/12/19 14:16, Thomas Huth wrote:
> On 03/12/2019 14.04, Paolo Bonzini wrote:
>> On 03/12/19 10:15, Thomas Huth wrote:
>>>>>> Maybe we can rename this as read_boot_order_mm, and the previous
>>>>>> read_boot_order_pc as read_boot_order_io.
>>>>>
>>>>> I don't think it makes much sense. This was completely specific to the
>>>>> "prep" machine, even the "40p" machine seems to prefer fw_cfg nowadays.
>>>>> So let's simply remove this old stuff.
>>>>>
>>>>>> diff --git a/tests/endianness-test.c b/tests/endianness-test.c
>>>>>> index 58527952a5..2798802c63 100644
>>>>>> --- a/tests/endianness-test.c
>>>>>> +++ b/tests/endianness-test.c
>>>>>> @@ -35,7 +35,7 @@ static const TestCase test_cases[] = {
>>>>>> { "mips64", "malta", 0x10000000, .bswap = true },
>>>>>> { "mips64el", "fulong2e", 0x1fd00000 },
>>>>>> { "ppc", "g3beige", 0xfe000000, .bswap = true, .superio =
>>>>>> "i82378" },
>>>>>> - { "ppc", "prep", 0x80000000, .bswap = true },
>>>>>> + { "ppc", "40p", 0x80000000, .bswap = true },
>>>>
>>>> ... here you access the Super I/O behind the PCI bridge via MMIO?
>>>
>>> The difference is that this is an *arbitrary* address in I/O space
>>> there.
>>
>> No, it's the base address of the ISA space, to which the tests add the
>> address of the pc-testdev device. It's not any different from the
>> 0x80000000 in boot-order-test.
>
> Hmm, interesting. Why is it not necessary to set up the BARs of the
> PCI-to-ISA bridge in this case?
I don't know. Maybe the machine doesn't need it, since these are not
really BARs, since they are positive-decode addresses on the ISA bus.
It may also be an emulation inaccuracy in the pc87312 ISA bridge.
Paolo
>> That said, I think it's a sensible objection that boot order doesn't
>> come from m48t59 on 40p (does it not?).
> Right. I'm also not an expert here, but I think the OpenBIOS on 40p
> rather uses fw_cfg instead.
>
> Thomas
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] hw/ppc/prep: Remove the deprecated "prep" machine and the OpenHackware BIOS
2019-12-03 8:25 ` Thomas Huth
2019-12-03 8:51 ` Philippe Mathieu-Daudé
@ 2019-12-03 22:36 ` Mark Cave-Ayland
1 sibling, 0 replies; 12+ messages in thread
From: Mark Cave-Ayland @ 2019-12-03 22:36 UTC (permalink / raw)
To: Thomas Huth, Philippe Mathieu-Daudé,
qemu-devel, David Gibson, Hervé Poussineau
Cc: Laurent Vivier
On 03/12/2019 08:25, Thomas Huth wrote:
> On 03/12/2019 08.45, Philippe Mathieu-Daudé wrote:
>> On 12/3/19 8:29 AM, Thomas Huth wrote:
>>> It's been deprecated since QEMU v3.1. The 40p machine should be
>>> used nowadays instead.
>>>
>>> Signed-off-by: Thomas Huth <thuth@redhat.com>
>>> ---
>>> .gitmodules | 3 -
>>> MAINTAINERS | 1 -
>>> Makefile | 2 +-
>>> docs/interop/firmware.json | 3 +-
>>> hw/ppc/ppc.c | 18 --
>>> hw/ppc/prep.c | 384 +------------------------------------
>>> include/hw/ppc/ppc.h | 1 -
>>> pc-bios/README | 3 -
>>> pc-bios/ppc_rom.bin | Bin 1048576 -> 0 bytes
>>> qemu-deprecated.texi | 6 -
>>> qemu-doc.texi | 15 +-
>>> roms/openhackware | 1 -
>>> tests/boot-order-test.c | 25 ---
>>> tests/cdrom-test.c | 2 +-
>>> tests/endianness-test.c | 2 +-
>>> 15 files changed, 10 insertions(+), 456 deletions(-)
>>> delete mode 100644 pc-bios/ppc_rom.bin
>>> delete mode 160000 roms/openhackware
>> [...]
>>> diff --git a/tests/boot-order-test.c b/tests/boot-order-test.c
>>> index a725bce729..4a6218a516 100644
>>> --- a/tests/boot-order-test.c
>>> +++ b/tests/boot-order-test.c
>>> @@ -108,30 +108,6 @@ static void test_pc_boot_order(void)
>>> test_boot_orders(NULL, read_boot_order_pc, test_cases_pc);
>>> }
>>> -static uint8_t read_m48t59(QTestState *qts, uint64_t addr, uint16_t
>>> reg)
>>> -{
>>> - qtest_writeb(qts, addr, reg & 0xff);
>>> - qtest_writeb(qts, addr + 1, reg >> 8);
>>> - return qtest_readb(qts, addr + 3);
>>> -}
>>> -
>>> -static uint64_t read_boot_order_prep(QTestState *qts)
>>> -{
>>> - return read_m48t59(qts, 0x80000000 + 0x74, 0x34);
>>
>> I'd rather keep this generic mmio-mapped ISA test.
>> Maybe run it with the 40p machine?
>
> I don't think that this is possible in an easy way here. On the prep
> machine, the ISA bus is on a hard-coded MMIO address. On the 40p
> machine, the ISA bus is behind a PCI-to-ISA bridge, thus the PCI part
> needs to be set up first.
FWIW for sun4u we already cheat a bit here: the ebus device is the first PCI device
behind the PCI bridge which uses IO space, and so we know that this ultimately gets
mapped to the start of the IO memory space. We also configure the PCI bridge in QEMU
so that it allows IO accesses by default which means we also get the early console
before PCI bus enumeration.
>> Maybe we can rename this as read_boot_order_mm, and the previous
>> read_boot_order_pc as read_boot_order_io.
>
> I don't think it makes much sense. This was completely specific to the
> "prep" machine, even the "40p" machine seems to prefer fw_cfg nowadays.
> So let's simply remove this old stuff.
From memory there were some issues with fw_cfg because the prep (OHW) and 40p
(OpenBIOS) machines had different NVRAM layouts. Once the prep machine has been
removed it should be easy to fix though.
ATB,
Mark.
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] hw/ppc/prep: Remove the deprecated "prep" machine and the OpenHackware BIOS
2019-12-03 7:29 [PATCH] hw/ppc/prep: Remove the deprecated "prep" machine and the OpenHackware BIOS Thomas Huth
2019-12-03 7:45 ` Philippe Mathieu-Daudé
@ 2020-01-07 9:22 ` Thomas Huth
2020-01-07 21:21 ` Hervé Poussineau
1 sibling, 1 reply; 12+ messages in thread
From: Thomas Huth @ 2020-01-07 9:22 UTC (permalink / raw)
To: Hervé Poussineau; +Cc: qemu-devel, David Gibson
On 03/12/2019 08.29, Thomas Huth wrote:
> It's been deprecated since QEMU v3.1. The 40p machine should be
> used nowadays instead.
>
> Signed-off-by: Thomas Huth <thuth@redhat.com>
> ---
> .gitmodules | 3 -
> MAINTAINERS | 1 -
> Makefile | 2 +-
> docs/interop/firmware.json | 3 +-
> hw/ppc/ppc.c | 18 --
> hw/ppc/prep.c | 384 +------------------------------------
> include/hw/ppc/ppc.h | 1 -
> pc-bios/README | 3 -
> pc-bios/ppc_rom.bin | Bin 1048576 -> 0 bytes
> qemu-deprecated.texi | 6 -
> qemu-doc.texi | 15 +-
> roms/openhackware | 1 -
> tests/boot-order-test.c | 25 ---
> tests/cdrom-test.c | 2 +-
> tests/endianness-test.c | 2 +-
> 15 files changed, 10 insertions(+), 456 deletions(-)
> delete mode 100644 pc-bios/ppc_rom.bin
> delete mode 160000 roms/openhackware
>
> diff --git a/.gitmodules b/.gitmodules
> index 19792c9a11..9c0501a4d4 100644
> --- a/.gitmodules
> +++ b/.gitmodules
> @@ -10,9 +10,6 @@
> [submodule "roms/openbios"]
> path = roms/openbios
> url = https://git.qemu.org/git/openbios.git
> -[submodule "roms/openhackware"]
> - path = roms/openhackware
> - url = https://git.qemu.org/git/openhackware.git
> [submodule "roms/qemu-palcode"]
> path = roms/qemu-palcode
> url = https://git.qemu.org/git/qemu-palcode.git
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 5e5e3e52d6..9a9dee0fa4 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1081,7 +1081,6 @@ F: hw/dma/i82374.c
> F: hw/rtc/m48t59-isa.c
> F: include/hw/isa/pc87312.h
> F: include/hw/rtc/m48t59.h
> -F: pc-bios/ppc_rom.bin
> F: tests/acceptance/ppc_prep_40p.py
>
> sPAPR
> diff --git a/Makefile b/Makefile
> index b437a346d7..86476d1d9e 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -776,7 +776,7 @@ ifdef INSTALL_BLOBS
> BLOBS=bios.bin bios-256k.bin bios-microvm.bin sgabios.bin vgabios.bin vgabios-cirrus.bin \
> vgabios-stdvga.bin vgabios-vmware.bin vgabios-qxl.bin vgabios-virtio.bin \
> vgabios-ramfb.bin vgabios-bochs-display.bin vgabios-ati.bin \
> -ppc_rom.bin openbios-sparc32 openbios-sparc64 openbios-ppc QEMU,tcx.bin QEMU,cgthree.bin \
> +openbios-sparc32 openbios-sparc64 openbios-ppc QEMU,tcx.bin QEMU,cgthree.bin \
> pxe-e1000.rom pxe-eepro100.rom pxe-ne2k_pci.rom \
> pxe-pcnet.rom pxe-rtl8139.rom pxe-virtio.rom \
> efi-e1000.rom efi-eepro100.rom efi-ne2k_pci.rom \
> diff --git a/docs/interop/firmware.json b/docs/interop/firmware.json
> index 8ffb7856d2..240f565397 100644
> --- a/docs/interop/firmware.json
> +++ b/docs/interop/firmware.json
> @@ -27,8 +27,7 @@
> #
> # @openfirmware: The interface is defined by the (historical) IEEE
> # 1275-1994 standard. Examples for firmware projects that
> -# provide this interface are: OpenBIOS, OpenHackWare,
> -# SLOF.
> +# provide this interface are: OpenBIOS and SLOF.
> #
> # @uboot: Firmware interface defined by the U-Boot project.
> #
> diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
> index 52a18eb7d7..13b6cf85c0 100644
> --- a/hw/ppc/ppc.c
> +++ b/hw/ppc/ppc.c
> @@ -1476,24 +1476,6 @@ int ppc_dcr_init (CPUPPCState *env, int (*read_error)(int dcrn),
> }
>
> /*****************************************************************************/
> -/* Debug port */
> -void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val)
> -{
> - addr &= 0xF;
> - switch (addr) {
> - case 0:
> - printf("%c", val);
> - break;
> - case 1:
> - printf("\n");
> - fflush(stdout);
> - break;
> - case 2:
> - printf("Set loglevel to %04" PRIx32 "\n", val);
> - qemu_set_log(val | 0x100);
> - break;
> - }
> -}
>
> PowerPCCPU *ppc_get_vcpu_by_pir(int pir)
> {
> diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
> index 862345c2ac..111cc80867 100644
> --- a/hw/ppc/prep.c
> +++ b/hw/ppc/prep.c
> @@ -42,7 +42,7 @@
> #include "hw/loader.h"
> #include "hw/rtc/mc146818rtc.h"
> #include "hw/isa/pc87312.h"
> -#include "hw/net/ne2000-isa.h"
> +#include "hw/qdev-properties.h"
> #include "sysemu/arch_init.h"
> #include "sysemu/kvm.h"
> #include "sysemu/qtest.h"
> @@ -60,178 +60,9 @@
>
> #define CFG_ADDR 0xf0000510
>
> -#define BIOS_SIZE (1 * MiB)
> -#define BIOS_FILENAME "ppc_rom.bin"
> #define KERNEL_LOAD_ADDR 0x01000000
> #define INITRD_LOAD_ADDR 0x01800000
>
> -/* Constants for devices init */
> -static const int ide_iobase[2] = { 0x1f0, 0x170 };
> -static const int ide_iobase2[2] = { 0x3f6, 0x376 };
> -static const int ide_irq[2] = { 13, 13 };
> -
> -#define NE2000_NB_MAX 6
> -
> -static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
> -static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
> -
> -/* ISA IO ports bridge */
> -#define PPC_IO_BASE 0x80000000
> -
> -/* Fake super-io ports for PREP platform (Intel 82378ZB) */
> -typedef struct sysctrl_t {
> - qemu_irq reset_irq;
> - Nvram *nvram;
> - uint8_t state;
> - uint8_t syscontrol;
> - int contiguous_map;
> - qemu_irq contiguous_map_irq;
> - int endian;
> -} sysctrl_t;
> -
> -enum {
> - STATE_HARDFILE = 0x01,
> -};
> -
> -static sysctrl_t *sysctrl;
> -
> -static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
> -{
> - sysctrl_t *sysctrl = opaque;
> -
> - trace_prep_io_800_writeb(addr - PPC_IO_BASE, val);
> - switch (addr) {
> - case 0x0092:
> - /* Special port 92 */
> - /* Check soft reset asked */
> - if (val & 0x01) {
> - qemu_irq_raise(sysctrl->reset_irq);
> - } else {
> - qemu_irq_lower(sysctrl->reset_irq);
> - }
> - /* Check LE mode */
> - if (val & 0x02) {
> - sysctrl->endian = 1;
> - } else {
> - sysctrl->endian = 0;
> - }
> - break;
> - case 0x0800:
> - /* Motorola CPU configuration register : read-only */
> - break;
> - case 0x0802:
> - /* Motorola base module feature register : read-only */
> - break;
> - case 0x0803:
> - /* Motorola base module status register : read-only */
> - break;
> - case 0x0808:
> - /* Hardfile light register */
> - if (val & 1)
> - sysctrl->state |= STATE_HARDFILE;
> - else
> - sysctrl->state &= ~STATE_HARDFILE;
> - break;
> - case 0x0810:
> - /* Password protect 1 register */
> - if (sysctrl->nvram != NULL) {
> - NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
> - (k->toggle_lock)(sysctrl->nvram, 1);
> - }
> - break;
> - case 0x0812:
> - /* Password protect 2 register */
> - if (sysctrl->nvram != NULL) {
> - NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
> - (k->toggle_lock)(sysctrl->nvram, 2);
> - }
> - break;
> - case 0x0814:
> - /* L2 invalidate register */
> - // tlb_flush(first_cpu, 1);
> - break;
> - case 0x081C:
> - /* system control register */
> - sysctrl->syscontrol = val & 0x0F;
> - break;
> - case 0x0850:
> - /* I/O map type register */
> - sysctrl->contiguous_map = val & 0x01;
> - qemu_set_irq(sysctrl->contiguous_map_irq, sysctrl->contiguous_map);
> - break;
> - default:
> - printf("ERROR: unaffected IO port write: %04" PRIx32
> - " => %02" PRIx32"\n", addr, val);
> - break;
> - }
> -}
> -
> -static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
> -{
> - sysctrl_t *sysctrl = opaque;
> - uint32_t retval = 0xFF;
> -
> - switch (addr) {
> - case 0x0092:
> - /* Special port 92 */
> - retval = sysctrl->endian << 1;
> - break;
> - case 0x0800:
> - /* Motorola CPU configuration register */
> - retval = 0xEF; /* MPC750 */
> - break;
> - case 0x0802:
> - /* Motorola Base module feature register */
> - retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
> - break;
> - case 0x0803:
> - /* Motorola base module status register */
> - retval = 0xE0; /* Standard MPC750 */
> - break;
> - case 0x080C:
> - /* Equipment present register:
> - * no L2 cache
> - * no upgrade processor
> - * no cards in PCI slots
> - * SCSI fuse is bad
> - */
> - retval = 0x3C;
> - break;
> - case 0x0810:
> - /* Motorola base module extended feature register */
> - retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
> - break;
> - case 0x0814:
> - /* L2 invalidate: don't care */
> - break;
> - case 0x0818:
> - /* Keylock */
> - retval = 0x00;
> - break;
> - case 0x081C:
> - /* system control register
> - * 7 - 6 / 1 - 0: L2 cache enable
> - */
> - retval = sysctrl->syscontrol;
> - break;
> - case 0x0823:
> - /* */
> - retval = 0x03; /* no L2 cache */
> - break;
> - case 0x0850:
> - /* I/O map type register */
> - retval = sysctrl->contiguous_map;
> - break;
> - default:
> - printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
> - break;
> - }
> - trace_prep_io_800_readb(addr - PPC_IO_BASE, retval);
> -
> - return retval;
> -}
> -
> -
> #define NVRAM_SIZE 0x2000
>
> static void fw_cfg_boot_set(void *opaque, const char *boot_device,
> @@ -247,17 +78,6 @@ static void ppc_prep_reset(void *opaque)
> cpu_reset(CPU(cpu));
> }
>
> -static const MemoryRegionPortio prep_portio_list[] = {
> - /* System control ports */
> - { 0x0092, 1, 1, .read = PREP_io_800_readb, .write = PREP_io_800_writeb, },
> - { 0x0800, 0x52, 1,
> - .read = PREP_io_800_readb, .write = PREP_io_800_writeb, },
> - /* Special port to get debug messages from Open-Firmware */
> - { 0x0F00, 4, 1, .write = PPC_debug_write, },
> - PORTIO_END_OF_LIST(),
> -};
> -
> -static PortioList prep_port_list;
>
> /*****************************************************************************/
> /* NVRAM helpers */
> @@ -397,207 +217,6 @@ static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size,
> return 0;
> }
>
> -/* PowerPC PREP hardware initialisation */
> -static void ppc_prep_init(MachineState *machine)
> -{
> - ram_addr_t ram_size = machine->ram_size;
> - const char *kernel_filename = machine->kernel_filename;
> - const char *kernel_cmdline = machine->kernel_cmdline;
> - const char *initrd_filename = machine->initrd_filename;
> - const char *boot_device = machine->boot_order;
> - MemoryRegion *sysmem = get_system_memory();
> - PowerPCCPU *cpu = NULL;
> - CPUPPCState *env = NULL;
> - Nvram *m48t59;
> -#if 0
> - MemoryRegion *xcsr = g_new(MemoryRegion, 1);
> -#endif
> - int linux_boot, i, nb_nics1;
> - MemoryRegion *ram = g_new(MemoryRegion, 1);
> - uint32_t kernel_base, initrd_base;
> - long kernel_size, initrd_size;
> - DeviceState *dev;
> - PCIHostState *pcihost;
> - PCIBus *pci_bus;
> - PCIDevice *pci;
> - ISABus *isa_bus;
> - ISADevice *isa;
> - int ppc_boot_device;
> - DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
> -
> - sysctrl = g_malloc0(sizeof(sysctrl_t));
> -
> - linux_boot = (kernel_filename != NULL);
> -
> - /* init CPUs */
> - for (i = 0; i < machine->smp.cpus; i++) {
> - cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
> - env = &cpu->env;
> -
> - if (env->flags & POWERPC_FLAG_RTC_CLK) {
> - /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
> - cpu_ppc_tb_init(env, 7812500UL);
> - } else {
> - /* Set time-base frequency to 100 Mhz */
> - cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
> - }
> - qemu_register_reset(ppc_prep_reset, cpu);
> - }
> -
> - /* allocate RAM */
> - memory_region_allocate_system_memory(ram, NULL, "ppc_prep.ram", ram_size);
> - memory_region_add_subregion(sysmem, 0, ram);
> -
> - if (linux_boot) {
> - kernel_base = KERNEL_LOAD_ADDR;
> - /* now we can load the kernel */
> - kernel_size = load_image_targphys(kernel_filename, kernel_base,
> - ram_size - kernel_base);
> - if (kernel_size < 0) {
> - error_report("could not load kernel '%s'", kernel_filename);
> - exit(1);
> - }
> - /* load initrd */
> - if (initrd_filename) {
> - initrd_base = INITRD_LOAD_ADDR;
> - initrd_size = load_image_targphys(initrd_filename, initrd_base,
> - ram_size - initrd_base);
> - if (initrd_size < 0) {
> - error_report("could not load initial ram disk '%s'",
> - initrd_filename);
> - exit(1);
> - }
> - } else {
> - initrd_base = 0;
> - initrd_size = 0;
> - }
> - ppc_boot_device = 'm';
> - } else {
> - kernel_base = 0;
> - kernel_size = 0;
> - initrd_base = 0;
> - initrd_size = 0;
> - ppc_boot_device = '\0';
> - /* For now, OHW cannot boot from the network. */
> - for (i = 0; boot_device[i] != '\0'; i++) {
> - if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
> - ppc_boot_device = boot_device[i];
> - break;
> - }
> - }
> - if (ppc_boot_device == '\0') {
> - error_report("No valid boot device for Mac99 machine");
> - exit(1);
> - }
> - }
> -
> - if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
> - error_report("Only 6xx bus is supported on PREP machine");
> - exit(1);
> - }
> -
> - dev = qdev_create(NULL, "raven-pcihost");
> - if (bios_name == NULL) {
> - bios_name = BIOS_FILENAME;
> - }
> - qdev_prop_set_string(dev, "bios-name", bios_name);
> - qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
> - qdev_prop_set_bit(dev, "is-legacy-prep", true);
> - pcihost = PCI_HOST_BRIDGE(dev);
> - object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL);
> - qdev_init_nofail(dev);
> - pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
> - if (pci_bus == NULL) {
> - error_report("Couldn't create PCI host controller");
> - exit(1);
> - }
> - sysctrl->contiguous_map_irq = qdev_get_gpio_in(dev, 0);
> -
> - /* PCI -> ISA bridge */
> - pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378");
> - cpu = POWERPC_CPU(first_cpu);
> - qdev_connect_gpio_out(&pci->qdev, 0,
> - cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
> - sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev, 9));
> - sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev, 11));
> - sysbus_connect_irq(&pcihost->busdev, 2, qdev_get_gpio_in(&pci->qdev, 9));
> - sysbus_connect_irq(&pcihost->busdev, 3, qdev_get_gpio_in(&pci->qdev, 11));
> - isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci), "isa.0"));
> -
> - /* Super I/O (parallel + serial ports) */
> - isa = isa_create(isa_bus, TYPE_PC87312_SUPERIO);
> - dev = DEVICE(isa);
> - qdev_prop_set_uint8(dev, "config", 13); /* fdc, ser0, ser1, par0 */
> - qdev_init_nofail(dev);
> -
> - /* init basic PC hardware */
> - pci_vga_init(pci_bus);
> -
> - nb_nics1 = nb_nics;
> - if (nb_nics1 > NE2000_NB_MAX)
> - nb_nics1 = NE2000_NB_MAX;
> - for(i = 0; i < nb_nics1; i++) {
> - if (nd_table[i].model == NULL) {
> - nd_table[i].model = g_strdup("ne2k_isa");
> - }
> - if (strcmp(nd_table[i].model, "ne2k_isa") == 0) {
> - isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i],
> - &nd_table[i]);
> - } else {
> - pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
> - }
> - }
> -
> - ide_drive_get(hd, ARRAY_SIZE(hd));
> - for(i = 0; i < MAX_IDE_BUS; i++) {
> - isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i],
> - hd[2 * i],
> - hd[2 * i + 1]);
> - }
> -
> - cpu = POWERPC_CPU(first_cpu);
> - sysctrl->reset_irq = cpu->env.irq_inputs[PPC6xx_INPUT_HRESET];
> -
> - portio_list_init(&prep_port_list, NULL, prep_portio_list, sysctrl, "prep");
> - portio_list_add(&prep_port_list, isa_address_space_io(isa), 0x0);
> -
> - /*
> - * PowerPC control and status register group: unimplemented,
> - * would be at address 0xFEFF0000.
> - */
> -
> - if (machine_usb(machine)) {
> - pci_create_simple(pci_bus, -1, "pci-ohci");
> - }
> -
> - m48t59 = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 2000, 59);
> - if (m48t59 == NULL)
> - return;
> - sysctrl->nvram = m48t59;
> -
> - /* Initialise NVRAM */
> - PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size,
> - ppc_boot_device,
> - kernel_base, kernel_size,
> - kernel_cmdline,
> - initrd_base, initrd_size,
> - /* XXX: need an option to load a NVRAM image */
> - 0,
> - graphic_width, graphic_height, graphic_depth);
> -}
> -
> -static void prep_machine_init(MachineClass *mc)
> -{
> - mc->deprecation_reason = "use 40p machine type instead";
> - mc->desc = "PowerPC PREP platform";
> - mc->init = ppc_prep_init;
> - mc->block_default_type = IF_IDE;
> - mc->max_cpus = MAX_CPUS;
> - mc->default_boot_order = "cad";
> - mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("602");
> - mc->default_display = "std";
> -}
> -
> static int prep_set_cmos_checksum(DeviceState *dev, void *opaque)
> {
> uint16_t checksum = *(uint16_t *)opaque;
> @@ -821,4 +440,3 @@ static void ibm_40p_machine_init(MachineClass *mc)
> }
>
> DEFINE_MACHINE("40p", ibm_40p_machine_init)
> -DEFINE_MACHINE("prep", prep_machine_init)
> diff --git a/include/hw/ppc/ppc.h b/include/hw/ppc/ppc.h
> index 4bdcb8bacd..94b28f77f6 100644
> --- a/include/hw/ppc/ppc.h
> +++ b/include/hw/ppc/ppc.h
> @@ -67,7 +67,6 @@ clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq,
> void ppc40x_core_reset(PowerPCCPU *cpu);
> void ppc40x_chip_reset(PowerPCCPU *cpu);
> void ppc40x_system_reset(PowerPCCPU *cpu);
> -void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
>
> #if defined(CONFIG_USER_ONLY)
> static inline void ppc40x_irq_init(PowerPCCPU *cpu) {}
> diff --git a/pc-bios/README b/pc-bios/README
> index 830645c51f..062c11a9eb 100644
> --- a/pc-bios/README
> +++ b/pc-bios/README
> @@ -4,9 +4,6 @@
> - The VGA BIOS and the Cirrus VGA BIOS come from the LGPL VGA bios
> project (http://www.nongnu.org/vgabios/).
>
> -- The PowerPC Open Hack'Ware Open Firmware Compatible BIOS is
> - available at https://repo.or.cz/openhackware.git.
> -
> - OpenBIOS (http://www.openbios.org/) is a free (GPL v2) portable
> firmware implementation. The goal is to implement a 100% IEEE
> 1275-1994 (referred to as Open Firmware) compliant firmware.
> diff --git a/pc-bios/ppc_rom.bin b/pc-bios/ppc_rom.bin
> deleted file mode 100644
> index 174a24744b73fb2824f9b1e7c0078f4499e1e724..0000000000000000000000000000000000000000
> GIT binary patch
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>
> diff --git a/qemu-deprecated.texi b/qemu-deprecated.texi
> index 4b4b7425ac..66d2b22a94 100644
> --- a/qemu-deprecated.texi
> +++ b/qemu-deprecated.texi
> @@ -271,12 +271,6 @@ The 'scsi-disk' device is deprecated. Users should use 'scsi-hd' or
> These machine types are very old and likely can not be used for live migration
> from old QEMU versions anymore. A newer machine type should be used instead.
>
> -@subsection prep (PowerPC) (since 3.1)
> -
> -This machine type uses an unmaintained firmware, broken in lots of ways,
> -and unable to start post-2004 operating systems. 40p machine type should be
> -used instead.
> -
> @subsection spike_v1.9.1 and spike_v1.10 (since 4.1)
>
> The version specific Spike machines have been deprecated in favour of the
> diff --git a/qemu-doc.texi b/qemu-doc.texi
> index 3ddf5c0a68..f8037f12ef 100644
> --- a/qemu-doc.texi
> +++ b/qemu-doc.texi
> @@ -1763,7 +1763,7 @@ differences are mentioned in the following sections.
> @section PowerPC System emulator
> @cindex system emulation (PowerPC)
>
> -Use the executable @file{qemu-system-ppc} to simulate a complete PREP
> +Use the executable @file{qemu-system-ppc} to simulate a complete 40P (PREP)
> or PowerMac PowerPC system.
>
> QEMU emulates the following PowerMac peripherals:
> @@ -1783,7 +1783,7 @@ Non Volatile RAM
> VIA-CUDA with ADB keyboard and mouse.
> @end itemize
>
> -QEMU emulates the following PREP peripherals:
> +QEMU emulates the following 40P (PREP) peripherals:
>
> @itemize @minus
> @item
> @@ -1795,7 +1795,7 @@ PCI VGA compatible card with VESA Bochs Extensions
> @item
> Floppy disk
> @item
> -NE2000 network adapters
> +PCnet network adapters
> @item
> Serial port
> @item
> @@ -1804,12 +1804,9 @@ PREP Non Volatile RAM
> PC compatible keyboard and mouse.
> @end itemize
>
> -QEMU uses the Open Hack'Ware Open Firmware Compatible BIOS available at
> -@url{http://perso.magic.fr/l_indien/OpenHackWare/index.htm}.
> -
> Since version 0.9.1, QEMU uses OpenBIOS @url{https://www.openbios.org/}
> -for the g3beige and mac99 PowerMac machines. OpenBIOS is a free (GPL
> -v2) portable firmware implementation. The goal is to implement a 100%
> +for the g3beige and mac99 PowerMac and the 40p machines. OpenBIOS is a free
> +(GPL v2) portable firmware implementation. The goal is to implement a 100%
> IEEE 1275-1994 (referred to as Open Firmware) compliant firmware.
>
> @c man begin OPTIONS
> @@ -1832,8 +1829,6 @@ qemu-system-ppc -prom-env 'auto-boot?=false' \
> -prom-env 'boot-args=conf=hd:2,\yaboot.conf'
> @end example
>
> -These variables are not used by Open Hack'Ware.
> -
> @end table
>
> @c man end
> diff --git a/roms/openhackware b/roms/openhackware
> deleted file mode 160000
> index c559da7c8e..0000000000
> --- a/roms/openhackware
> +++ /dev/null
> @@ -1 +0,0 @@
> -Subproject commit c559da7c8eec5e45ef1f67978827af6f0b9546f5
> diff --git a/tests/boot-order-test.c b/tests/boot-order-test.c
> index a725bce729..4a6218a516 100644
> --- a/tests/boot-order-test.c
> +++ b/tests/boot-order-test.c
> @@ -108,30 +108,6 @@ static void test_pc_boot_order(void)
> test_boot_orders(NULL, read_boot_order_pc, test_cases_pc);
> }
>
> -static uint8_t read_m48t59(QTestState *qts, uint64_t addr, uint16_t reg)
> -{
> - qtest_writeb(qts, addr, reg & 0xff);
> - qtest_writeb(qts, addr + 1, reg >> 8);
> - return qtest_readb(qts, addr + 3);
> -}
> -
> -static uint64_t read_boot_order_prep(QTestState *qts)
> -{
> - return read_m48t59(qts, 0x80000000 + 0x74, 0x34);
> -}
> -
> -static const boot_order_test test_cases_prep[] = {
> - { "", 'c', 'c' },
> - { "-boot c", 'c', 'c' },
> - { "-boot d", 'd', 'd' },
> - {}
> -};
> -
> -static void test_prep_boot_order(void)
> -{
> - test_boot_orders("prep", read_boot_order_prep, test_cases_prep);
> -}
> -
> static uint64_t read_boot_order_pmac(QTestState *qts)
> {
> QFWCFG *fw_cfg = mm_fw_cfg_init(qts, 0xf0000510);
> @@ -190,7 +166,6 @@ int main(int argc, char *argv[])
> if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) {
> qtest_add_func("boot-order/pc", test_pc_boot_order);
> } else if (strcmp(arch, "ppc") == 0 || strcmp(arch, "ppc64") == 0) {
> - qtest_add_func("boot-order/prep", test_prep_boot_order);
> qtest_add_func("boot-order/pmac_oldworld",
> test_pmac_oldworld_boot_order);
> qtest_add_func("boot-order/pmac_newworld",
> diff --git a/tests/cdrom-test.c b/tests/cdrom-test.c
> index 34e9974634..006044f48a 100644
> --- a/tests/cdrom-test.c
> +++ b/tests/cdrom-test.c
> @@ -189,7 +189,7 @@ int main(int argc, char **argv)
> add_s390x_tests();
> } else if (g_str_equal(arch, "ppc64")) {
> const char *ppcmachines[] = {
> - "pseries", "mac99", "g3beige", "40p", "prep", NULL
> + "pseries", "mac99", "g3beige", "40p", NULL
> };
> add_cdrom_param_tests(ppcmachines);
> } else if (g_str_equal(arch, "sparc")) {
> diff --git a/tests/endianness-test.c b/tests/endianness-test.c
> index 58527952a5..2798802c63 100644
> --- a/tests/endianness-test.c
> +++ b/tests/endianness-test.c
> @@ -35,7 +35,7 @@ static const TestCase test_cases[] = {
> { "mips64", "malta", 0x10000000, .bswap = true },
> { "mips64el", "fulong2e", 0x1fd00000 },
> { "ppc", "g3beige", 0xfe000000, .bswap = true, .superio = "i82378" },
> - { "ppc", "prep", 0x80000000, .bswap = true },
> + { "ppc", "40p", 0x80000000, .bswap = true },
> { "ppc", "bamboo", 0xe8000000, .bswap = true, .superio = "i82378" },
> { "ppc64", "mac99", 0xf2000000, .bswap = true, .superio = "i82378" },
> { "ppc64", "pseries", (1ULL << 45), .bswap = true, .superio = "i82378" },
>
Ping ... Hervé, what do you think about the patch?
Thomas
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] hw/ppc/prep: Remove the deprecated "prep" machine and the OpenHackware BIOS
2020-01-07 9:22 ` Thomas Huth
@ 2020-01-07 21:21 ` Hervé Poussineau
0 siblings, 0 replies; 12+ messages in thread
From: Hervé Poussineau @ 2020-01-07 21:21 UTC (permalink / raw)
To: Thomas Huth; +Cc: qemu-devel, David Gibson
Le 07/01/2020 à 10:22, Thomas Huth a écrit :
> On 03/12/2019 08.29, Thomas Huth wrote:
>> It's been deprecated since QEMU v3.1. The 40p machine should be
>> used nowadays instead.
>>
>> Signed-off-by: Thomas Huth <thuth@redhat.com>
>> ---
>> .gitmodules | 3 -
>> MAINTAINERS | 1 -
>> Makefile | 2 +-
>> docs/interop/firmware.json | 3 +-
>> hw/ppc/ppc.c | 18 --
>> hw/ppc/prep.c | 384 +------------------------------------
>> include/hw/ppc/ppc.h | 1 -
>> pc-bios/README | 3 -
>> pc-bios/ppc_rom.bin | Bin 1048576 -> 0 bytes
>> qemu-deprecated.texi | 6 -
>> qemu-doc.texi | 15 +-
>> roms/openhackware | 1 -
>> tests/boot-order-test.c | 25 ---
>> tests/cdrom-test.c | 2 +-
>> tests/endianness-test.c | 2 +-
>> 15 files changed, 10 insertions(+), 456 deletions(-)
>> delete mode 100644 pc-bios/ppc_rom.bin
>> delete mode 160000 roms/openhackware
>>
[...]
>
> Ping ... Hervé, what do you think about the patch?
Hello Thomas,
I completely agree with this welcomed patch!
Acked-by: Hervé Poussineau <hpoussin@reactos.org>
Regards,
Hervé
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2020-01-07 21:22 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-12-03 7:29 [PATCH] hw/ppc/prep: Remove the deprecated "prep" machine and the OpenHackware BIOS Thomas Huth
2019-12-03 7:45 ` Philippe Mathieu-Daudé
2019-12-03 8:25 ` Thomas Huth
2019-12-03 8:51 ` Philippe Mathieu-Daudé
2019-12-03 9:15 ` Thomas Huth
2019-12-03 9:21 ` Philippe Mathieu-Daudé
2019-12-03 13:04 ` Paolo Bonzini
2019-12-03 13:16 ` Thomas Huth
2019-12-03 13:39 ` Paolo Bonzini
2019-12-03 22:36 ` Mark Cave-Ayland
2020-01-07 9:22 ` Thomas Huth
2020-01-07 21:21 ` Hervé Poussineau
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