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[76.210.143.223]) by smtp.gmail.com with ESMTPSA id 63sm61056pfv.25.2020.10.19.16.17.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Oct 2020 16:17:45 -0700 (PDT) Date: Mon, 19 Oct 2020 16:17:45 -0700 (PDT) X-Google-Original-Date: Mon, 19 Oct 2020 14:38:22 PDT (-0700) Subject: Re: [PATCH v2 1/4] hw/riscv: sifive_u: Allow specifying the CPU In-Reply-To: From: Palmer Dabbelt To: Alistair Francis Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::644; envelope-from=palmer@dabbelt.com; helo=mail-pl1-x644.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , bmeng.cn@gmail.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, alistair23@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, 13 Oct 2020 17:17:25 PDT (-0700), Alistair Francis wrote: > Allow the user to specify the main application CPU for the sifive_u > machine. > > Signed-off-by: Alistair Francis > Reviewed-by: Bin Meng > --- > include/hw/riscv/sifive_u.h | 1 + > hw/riscv/sifive_u.c | 18 +++++++++++++----- > 2 files changed, 14 insertions(+), 5 deletions(-) > > diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h > index 22e7e6efa1..a9f7b4a084 100644 > --- a/include/hw/riscv/sifive_u.h > +++ b/include/hw/riscv/sifive_u.h > @@ -48,6 +48,7 @@ typedef struct SiFiveUSoCState { > CadenceGEMState gem; > > uint32_t serial; > + char *cpu_type; > } SiFiveUSoCState; > > #define TYPE_RISCV_U_MACHINE MACHINE_TYPE_NAME("sifive_u") > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index 6ad975d692..5f3ad9bc0f 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -424,6 +424,8 @@ static void sifive_u_machine_init(MachineState *machine) > object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC); > object_property_set_uint(OBJECT(&s->soc), "serial", s->serial, > &error_abort); > + object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type, > + &error_abort); > qdev_realize(DEVICE(&s->soc), NULL, &error_abort); > > /* register RAM */ > @@ -590,6 +592,11 @@ static void sifive_u_machine_class_init(ObjectClass *oc, void *data) > mc->init = sifive_u_machine_init; > mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT; > mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; > +#if defined(TARGET_RISCV32) > + mc->default_cpu_type = TYPE_RISCV_CPU_SIFIVE_U34; > +#elif defined(TARGET_RISCV64) > + mc->default_cpu_type = TYPE_RISCV_CPU_SIFIVE_U54; > +#endif > mc->default_cpus = mc->min_cpus; > > object_class_property_add_bool(oc, "start-in-flash", > @@ -618,7 +625,6 @@ type_init(sifive_u_machine_init_register_types) > > static void sifive_u_soc_instance_init(Object *obj) > { > - MachineState *ms = MACHINE(qdev_get_machine()); > SiFiveUSoCState *s = RISCV_U_SOC(obj); > > object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER); > @@ -636,10 +642,6 @@ static void sifive_u_soc_instance_init(Object *obj) > > object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus, > TYPE_RISCV_HART_ARRAY); > - qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); > - qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); > - qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", SIFIVE_U_CPU); > - qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004); > > object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI); > object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP); > @@ -661,6 +663,11 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp) > int i; > NICInfo *nd = &nd_table[0]; > > + qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); > + qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); > + qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type); > + qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004); > + > sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort); > sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort); > /* > @@ -792,6 +799,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp) > > static Property sifive_u_soc_props[] = { > DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL), > + DEFINE_PROP_STRING("cpu-type", SiFiveUSoCState, cpu_type), > DEFINE_PROP_END_OF_LIST() > }; Reviewed-by: Palmer Dabbelt