From: Palmer Dabbelt <palmerdabbelt@google.com>
To: Alistair Francis <Alistair.Francis@wdc.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
Alistair Francis <Alistair.Francis@wdc.com>,
alistair23@gmail.com
Subject: Re: [PATCH v2 27/35] target/riscv: Mark both sstatus and msstatus_hs as dirty
Date: Thu, 13 Feb 2020 10:44:07 -0800 (PST) [thread overview]
Message-ID: <mhng-47cdaa98-793e-4dd1-8307-f53d1daec9e1@palmerdabbelt-glaptop1> (raw)
In-Reply-To: <5f3b8fd9e9743c13fd9e40bf811303bc2937667a.1580518859.git.alistair.francis@wdc.com>
On Fri, 31 Jan 2020 17:02:46 PST (-0800), Alistair Francis wrote:
> Mark both sstatus and vsstatus as dirty (3).
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/translate.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index afa2d6eea2..61fe9f03be 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -44,6 +44,7 @@ typedef struct DisasContext {
> /* pc_succ_insn points to the instruction following base.pc_next */
> target_ulong pc_succ_insn;
> target_ulong priv_ver;
> + bool virt_enabled;
> uint32_t opcode;
> uint32_t mstatus_fs;
> uint32_t misa;
> @@ -396,6 +397,12 @@ static void mark_fs_dirty(DisasContext *ctx)
> tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
> tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD);
> tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
> +
> + if (ctx->virt_enabled) {
> + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
> + tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD);
> + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
> + }
I suppose we could #ifdef this, but I don't think it's worth it.
> tcg_temp_free(tmp);
> }
> #else
> @@ -740,6 +747,11 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK;
> ctx->mstatus_fs = ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS;
> ctx->priv_ver = env->priv_ver;
> +#if !defined(CONFIG_USER_ONLY)
> + ctx->virt_enabled = riscv_cpu_virt_enabled(env);
> +#else
> + ctx->virt_enabled = false;
> +#endif
> ctx->misa = env->misa;
> ctx->frm = -1; /* unknown rounding mode */
> ctx->ext_ifencei = cpu->cfg.ext_ifencei;
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
next prev parent reply other threads:[~2020-02-13 18:49 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-01 1:01 [PATCH v2 00/35] Add RISC-V Hypervisor Extension v0.5 Alistair Francis
2020-02-01 1:01 ` [PATCH v2 01/35] target/riscv: Convert MIP CSR to target_ulong Alistair Francis
2020-02-01 1:01 ` [PATCH v2 02/35] target/riscv: Add the Hypervisor extension Alistair Francis
2020-02-01 1:01 ` [PATCH v2 03/35] target/riscv: Add the Hypervisor CSRs to CPUState Alistair Francis
2020-02-01 1:01 ` [PATCH v2 04/35] target/riscv: Add support for the new execption numbers Alistair Francis
2020-02-01 1:01 ` [PATCH v2 05/35] target/riscv: Rename the H irqs to VS irqs Alistair Francis
2020-02-01 1:01 ` [PATCH v2 06/35] target/riscv: Add the virtulisation mode Alistair Francis
2020-02-01 1:01 ` [PATCH v2 07/35] target/riscv: Add the force HS exception mode Alistair Francis
2020-02-10 21:46 ` Palmer Dabbelt
2020-02-01 1:01 ` [PATCH v2 08/35] target/riscv: Fix CSR perm checking for HS mode Alistair Francis
2020-02-01 1:01 ` [PATCH v2 09/35] target/riscv: Print priv and virt in disas log Alistair Francis
2020-02-01 1:02 ` [PATCH v2 10/35] target/riscv: Dump Hypervisor registers if enabled Alistair Francis
2020-02-01 1:02 ` [PATCH v2 11/35] target/riscv: Add Hypervisor CSR access functions Alistair Francis
2020-02-01 1:02 ` [PATCH v2 12/35] target/riscv: Add Hypervisor virtual CSRs accesses Alistair Francis
2020-02-01 1:02 ` [PATCH v2 13/35] target/riscv: Add Hypervisor machine " Alistair Francis
2020-02-01 1:02 ` [PATCH v2 14/35] target/riscv: Add virtual register swapping function Alistair Francis
2020-02-01 1:02 ` [PATCH v2 15/35] target/riscv: Set VS bits in mideleg for Hyp extension Alistair Francis
2020-02-01 1:02 ` [PATCH v2 16/35] target/riscv: Extend the MIE CSR to support virtulisation Alistair Francis
2020-02-01 1:02 ` [PATCH v2 17/35] target/riscv: Extend the SIP " Alistair Francis
2020-02-01 1:02 ` [PATCH v2 18/35] target/riscv: Add support for virtual interrupt setting Alistair Francis
2020-02-01 1:02 ` [PATCH v2 19/35] target/ricsv: Flush the TLB on virtulisation mode changes Alistair Francis
2020-02-01 1:02 ` [PATCH v2 20/35] target/riscv: Generate illegal instruction on WFI when V=1 Alistair Francis
2020-02-01 1:02 ` [PATCH v2 21/35] target/riscv: Add hypvervisor trap support Alistair Francis
2020-02-12 20:03 ` Palmer Dabbelt
2020-02-01 1:02 ` [PATCH v2 22/35] target/riscv: Add Hypervisor trap return support Alistair Francis
2020-02-01 1:02 ` [PATCH v2 23/35] target/riscv: Add hfence instructions Alistair Francis
2020-02-01 1:02 ` [PATCH v2 24/35] target/riscv: Remove the hret instruction Alistair Francis
2020-02-01 1:02 ` [PATCH v2 25/35] target/riscv: Only set TB flags with FP status if enabled Alistair Francis
2020-02-13 18:31 ` Palmer Dabbelt
2020-02-01 1:02 ` [PATCH v2 26/35] target/riscv: Disable guest FP support based on virtual status Alistair Francis
2020-02-13 18:39 ` Palmer Dabbelt
2020-02-01 1:02 ` [PATCH v2 27/35] target/riscv: Mark both sstatus and msstatus_hs as dirty Alistair Francis
2020-02-13 18:44 ` Palmer Dabbelt [this message]
2020-02-01 1:02 ` [PATCH v2 28/35] target/riscv: Respect MPRV and SPRV for floating point ops Alistair Francis
2020-02-01 1:02 ` [PATCH v2 29/35] target/riscv: Allow specifying MMU stage Alistair Francis
2020-02-01 1:02 ` [PATCH v2 30/35] target/riscv: Implement second stage MMU Alistair Francis
2020-02-01 1:02 ` [PATCH v2 31/35] target/riscv: Raise the new execptions when 2nd stage translation fails Alistair Francis
2020-02-01 1:03 ` [PATCH v2 32/35] target/riscv: Set htval and mtval2 on execptions Alistair Francis
2020-02-01 1:03 ` [PATCH v2 33/35] target/riscv: Add support for the 32-bit MSTATUSH CSR Alistair Francis
2020-02-17 19:04 ` Palmer Dabbelt
2020-02-01 1:03 ` [PATCH v2 34/35] target/riscv: Add the MSTATUS_MPV_ISSET helper macro Alistair Francis
2020-02-01 1:03 ` [PATCH v2 35/35] target/riscv: Allow enabling the Hypervisor extension Alistair Francis
2020-02-10 18:50 ` [PATCH v2 00/35] Add RISC-V Hypervisor Extension v0.5 Palmer Dabbelt
2020-02-10 19:52 ` Alistair Francis
2020-02-17 19:11 ` Palmer Dabbelt
2020-02-18 18:11 ` Alistair Francis
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