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Mon, 09 Sep 2019 09:20:55 -0700 (PDT) Received: from localhost ([148.69.85.38]) by smtp.gmail.com with ESMTPSA id z1sm24856457wre.40.2019.09.09.09.20.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Sep 2019 09:20:55 -0700 (PDT) Date: Mon, 09 Sep 2019 09:20:55 -0700 (PDT) X-Google-Original-Date: Mon, 09 Sep 2019 09:04:19 PDT (-0700) In-Reply-To: <1567786819-22142-2-git-send-email-bmeng.cn@gmail.com> From: Palmer Dabbelt To: bmeng.cn@gmail.com Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.128.67 Subject: Re: [Qemu-devel] [PATCH v8 01/32] riscv: hw: Remove duplicated "hw/hw.h" inclusion X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Alistair Francis , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Fri, 06 Sep 2019 09:19:48 PDT (-0700), bmeng.cn@gmail.com wrote: > Commit a27bd6c779ba ("Include hw/qdev-properties.h less") wrongly > added "hw/hw.h" to sifive_prci.c and sifive_test.c. > > Another inclusion of "hw/hw.h" was later added via > commit 650d103d3ea9 ("Include hw/hw.h exactly where needed"), that > resulted in duplicated inclusion of "hw/hw.h". > > Fixes: a27bd6c779ba ("Include hw/qdev-properties.h less") > Signed-off-by: Bin Meng > > --- > > Changes in v8: > - newly included in v8 to ease patch inter dependencies > > hw/riscv/sifive_prci.c | 1 - > hw/riscv/sifive_test.c | 1 - > 2 files changed, 2 deletions(-) > > diff --git a/hw/riscv/sifive_prci.c b/hw/riscv/sifive_prci.c > index 9837b61..562bc3d 100644 > --- a/hw/riscv/sifive_prci.c > +++ b/hw/riscv/sifive_prci.c > @@ -19,7 +19,6 @@ > */ > > #include "qemu/osdep.h" > -#include "hw/hw.h" > #include "hw/sysbus.h" > #include "qemu/module.h" > #include "target/riscv/cpu.h" > diff --git a/hw/riscv/sifive_test.c b/hw/riscv/sifive_test.c > index afbb3aa..3a14f9f 100644 > --- a/hw/riscv/sifive_test.c > +++ b/hw/riscv/sifive_test.c > @@ -19,7 +19,6 @@ > */ > > #include "qemu/osdep.h" > -#include "hw/hw.h" > #include "hw/sysbus.h" > #include "qemu/module.h" > #include "target/riscv/cpu.h" Revieweb-by: Palmer Dabbelt