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Tue, 10 Sep 2019 07:48:08 -0700 (PDT) Date: Tue, 10 Sep 2019 07:48:08 -0700 (PDT) X-Google-Original-Date: Tue, 10 Sep 2019 07:44:11 PDT (-0700) In-Reply-To: <47e7fd90ce1d2373824799274376b29d751d56c3.1566603412.git.alistair.francis@wdc.com> From: Palmer Dabbelt To: Alistair Francis Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.221.68 Subject: Re: [Qemu-devel] [PATCH v1 07/28] target/riscv: Dump Hypervisor registers if enabled X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Anup Patel , qemu-devel@nongnu.org, Atish Patra , Alistair Francis , alistair23@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Fri, 23 Aug 2019 16:38:07 PDT (-0700), Alistair Francis wrote: > Dump the Hypervisor registers and the current Hypervisor state. > > While we are editing this code let's also dump stvec and scause. > > Signed-off-by: Alistair Francis > Signed-off-by: Atish Patra > --- > target/riscv/cpu.c | 34 ++++++++++++++++++++++++++++++++++ > 1 file changed, 34 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index f13e298a36..be8f643fc2 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -220,18 +220,52 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) > CPURISCVState *env = &cpu->env; > int i; > > +#if !defined(CONFIG_USER_ONLY) > + if (riscv_has_ext(env, RVH)) { > + qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); > + } > +#endif > qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); > #ifndef CONFIG_USER_ONLY > qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); > qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus); > + if (riscv_has_ext(env, RVH)) { > + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus); > + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "bstatus ", env->vsstatus); > + } > qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", > (target_ulong)atomic_read(&env->mip)); > + if (riscv_has_ext(env, RVH)) { > + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsip ", > + (target_ulong)atomic_read(&env->vsip)); > + } > qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie); > + if (riscv_has_ext(env, RVH)) { > + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsie ", env->vsie); > + } > qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg); > + if (riscv_has_ext(env, RVH)) { > + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg); > + } > qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg); > + if (riscv_has_ext(env, RVH)) { > + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg); > + } > qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec ", env->mtvec); > + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec ", env->stvec); > + if (riscv_has_ext(env, RVH)) { > + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec ", env->vstvec); > + } > qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc ", env->mepc); > + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc ", env->sepc); > + if (riscv_has_ext(env, RVH)) { > + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc ", env->vsepc); > + } > qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause ", env->mcause); > + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause ", env->scause); > + if (riscv_has_ext(env, RVH)) { > + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause); > + } > #endif > > for (i = 0; i < 32; i++) { Reviewed-by: Palmer Dabbelt