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From: Palmer Dabbelt <palmer@sifive.com>
To: frederic.konrad@adacore.com
Cc: "open list:RISC-V TCG CPUs" <qemu-riscv@nongnu.org>,
	sagark@eecs.berkeley.edu,
	Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	qemu-devel@nongnu.org, frederic.konrad@adacore.com,
	Alistair Francis <Alistair.Francis@wdc.com>
Subject: Re: [Qemu-devel] [PATCH v1] gdbstub: riscv: fix the fflags registers
Date: Fri, 13 Sep 2019 14:20:45 -0700 (PDT)
Message-ID: <mhng-b33d5ee5-58d7-402f-ad7f-e79f58ed84f7@palmer-si-x1e> (raw)
In-Reply-To: <1568103341-28636-1-git-send-email-frederic.konrad@adacore.com>

On Tue, 10 Sep 2019 01:15:41 PDT (-0700), frederic.konrad@adacore.com wrote:
> While debugging an application with GDB the following might happen:
>
> (gdb) return
> Make xxx return now? (y or n) y
> Could not fetch register "fflags"; remote failure reply 'E14'
>
> This is because riscv_gdb_get_fpu calls riscv_csrrw_debug with a wrong csr
> number (8). It should use the csr_register_map in order to reach the
> riscv_cpu_get_fflags callback.
>
> Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
> ---
>  target/riscv/gdbstub.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index 27be932..ded140e 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -313,7 +313,8 @@ static int riscv_gdb_get_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
>           * register 33, so we recalculate the map index.
>           * This also works for CSR_FRM and CSR_FCSR.
>           */
> -        result = riscv_csrrw_debug(env, n - 33 +  8, &val, 0, 0);
> +        result = riscv_csrrw_debug(env, n - 33 + csr_register_map[8], &val,
> +                                   0, 0);
>          if (result == 0) {
>              return gdb_get_regl(mem_buf, val);
>          }
> @@ -335,7 +336,8 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
>           * register 33, so we recalculate the map index.
>           * This also works for CSR_FRM and CSR_FCSR.
>           */
> -        result = riscv_csrrw_debug(env, n - 33 + 8, NULL, val, -1);
> +        result = riscv_csrrw_debug(env, n - 33 + csr_register_map[8], NULL,
> +                                   val, -1);
>          if (result == 0) {
>              return sizeof(target_ulong);
>          }

Reviewed-by: Palmer Dabbelt <palmer@sifive.com>

I just tagged a fixed version of my PR, but I'll include this in the next one.


  reply index

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-10  8:15 KONRAD Frederic
2019-09-13 21:20 ` Palmer Dabbelt [this message]
2019-09-16 21:29 ` Alistair Francis

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