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Tue, 10 Sep 2019 06:16:40 -0700 (PDT) Received: from localhost ([148.69.85.38]) by smtp.gmail.com with ESMTPSA id o22sm32214327wra.96.2019.09.10.06.16.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Sep 2019 06:16:34 -0700 (PDT) Date: Tue, 10 Sep 2019 06:16:34 -0700 (PDT) X-Google-Original-Date: Tue, 10 Sep 2019 06:15:11 PDT (-0700) In-Reply-To: From: Palmer Dabbelt To: Alistair Francis Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.221.67 Subject: Re: [Qemu-devel] [PATCH v4 0/7] RISC-V: Hypervisor prep work part 2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , bmeng.cn@gmail.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, alistair23@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Fri, 23 Aug 2019 08:21:06 PDT (-0700), Alistair Francis wrote: > > The first three patches are ones that I have pulled out of my original > Hypervisor series at an attempt to reduce the number of patches in the > series. > > These three patches all make sense without the Hypervisor series so can > be merged seperatley and will reduce the review burden of the next > version of the patches. > > The fource patch is a prep patch for the new v0.4 Hypervisor spec. > > The fifth patch is unreleated to Hypervisor that I'm just slipping in > here because it seems easier then sending it by itself. > > The final two patches are issues I discovered while adding the v0.4 > Hypervisor extension. > > v4: > - Drop MIP change patch > - Add a Floating Point fixup patch > v3: > - Change names of all GP registers > - Add two more patches > v2: > - Small corrections based on feedback > - Remove the CSR permission check patch > > > > Alistair Francis (6): > target/riscv: Don't set write permissions on dirty PTEs > riscv: plic: Remove unused interrupt functions > target/riscv: Create function to test if FP is enabled > target/riscv: Update the Hypervisor CSRs to v0.4 > target/riscv: Fix mstatus dirty mask > target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point > > Atish Patra (1): > target/riscv: Use both register name and ABI name > > hw/riscv/sifive_plic.c | 12 ------------ > include/hw/riscv/sifive_plic.h | 3 --- > target/riscv/cpu.c | 19 ++++++++++-------- > target/riscv/cpu.h | 6 +++++- > target/riscv/cpu_bits.h | 35 +++++++++++++++++----------------- > target/riscv/cpu_helper.c | 16 ++++++++++++---- > target/riscv/csr.c | 22 +++++++++++---------- > 7 files changed, 58 insertions(+), 55 deletions(-) Aside from that PTE patch, I've applied target/riscv: Use both register name and ABI name target/riscv: Fix mstatus dirty mask target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point on top of Bin's patch set, as the rest had made it into for-master. Like we talked about at lunch, I'm not sure the PTE one is actually correct -- it might just be paranoia, though.