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Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH v3 5/6] target/riscv: update APLIC and IMSIC to support KVM AIA Content-Language: en-US To: Yong-Xuan Wang , qemu-devel@nongnu.org, qemu-riscv@nongnu.org, rkanwal@rivosinc.com, anup@brainfault.org, atishp@atishpatra.org, vincent.chen@sifive.com, greentime.hu@sifive.com, frank.chang@sifive.com, jim.shu@sifive.com Cc: Alistair Francis , Stefan Weil , Mayuresh Chitale , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Andrew Jones , Palmer Dabbelt References: <20230526062509.31682-1-yongxuan.wang@sifive.com> <20230526062509.31682-6-yongxuan.wang@sifive.com> From: Daniel Henrique Barboza In-Reply-To: <20230526062509.31682-6-yongxuan.wang@sifive.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2001:4860:4864:20::30; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x30.google.com X-Spam_score_int: 11 X-Spam_score: 1.1 X-Spam_bar: + X-Spam_report: (1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.094, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On 5/26/23 03:25, Yong-Xuan Wang wrote: > - Do not set the mmio operations of APLIC and IMSIC when using KVM AIA > - Send interrupt signal to KVM AIA via KVM_IRQ_LINE API > > Signed-off-by: Yong-Xuan Wang > Reviewed-by: Jim Shu > --- Reviewed-by: Daniel Henrique Barboza > hw/intc/riscv_aplic.c | 19 +++++++++++++++---- > hw/intc/riscv_imsic.c | 16 +++++++++++----- > 2 files changed, 26 insertions(+), 9 deletions(-) > > diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c > index afc5b54dbb..adf5427f22 100644 > --- a/hw/intc/riscv_aplic.c > +++ b/hw/intc/riscv_aplic.c > @@ -31,6 +31,7 @@ > #include "hw/irq.h" > #include "target/riscv/cpu.h" > #include "sysemu/sysemu.h" > +#include "sysemu/kvm.h" > #include "migration/vmstate.h" > > #define APLIC_MAX_IDC (1UL << 14) > @@ -479,6 +480,11 @@ static void riscv_aplic_request(void *opaque, int irq, int level) > > assert((0 < irq) && (irq < aplic->num_irqs)); > > + if (kvm_irqchip_in_kernel()) { > + kvm_set_irq(kvm_state, irq, !!level); > + return; > + } > + > sourcecfg = aplic->sourcecfg[irq]; > if (sourcecfg & APLIC_SOURCECFG_D) { > childidx = sourcecfg & APLIC_SOURCECFG_CHILDIDX_MASK; > @@ -814,9 +820,11 @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp) > aplic->iforce = g_new0(uint32_t, aplic->num_harts); > aplic->ithreshold = g_new0(uint32_t, aplic->num_harts); > > - memory_region_init_io(&aplic->mmio, OBJECT(dev), &riscv_aplic_ops, aplic, > - TYPE_RISCV_APLIC, aplic->aperture_size); > - sysbus_init_mmio(SYS_BUS_DEVICE(dev), &aplic->mmio); > + if (!kvm_irqchip_in_kernel()) { > + memory_region_init_io(&aplic->mmio, OBJECT(dev), &riscv_aplic_ops, > + aplic, TYPE_RISCV_APLIC, aplic->aperture_size); > + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &aplic->mmio); > + } > > /* > * Only root APLICs have hardware IRQ lines. All non-root APLICs > @@ -958,7 +966,10 @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size, > qdev_prop_set_bit(dev, "mmode", mmode); > > sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); > - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); > + > + if (!kvm_irqchip_in_kernel()) { > + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); > + } > > if (parent) { > riscv_aplic_add_child(parent, dev); > diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c > index fea3385b51..8bfa480f7c 100644 > --- a/hw/intc/riscv_imsic.c > +++ b/hw/intc/riscv_imsic.c > @@ -32,6 +32,7 @@ > #include "target/riscv/cpu.h" > #include "target/riscv/cpu_bits.h" > #include "sysemu/sysemu.h" > +#include "sysemu/kvm.h" > #include "migration/vmstate.h" > > #define IMSIC_MMIO_PAGE_LE 0x00 > @@ -325,10 +326,12 @@ static void riscv_imsic_realize(DeviceState *dev, Error **errp) > imsic->eithreshold = g_new0(uint32_t, imsic->num_pages); > imsic->eistate = g_new0(uint32_t, imsic->num_eistate); > > - memory_region_init_io(&imsic->mmio, OBJECT(dev), &riscv_imsic_ops, > - imsic, TYPE_RISCV_IMSIC, > - IMSIC_MMIO_SIZE(imsic->num_pages)); > - sysbus_init_mmio(SYS_BUS_DEVICE(dev), &imsic->mmio); > + if (!kvm_irqchip_in_kernel()) { > + memory_region_init_io(&imsic->mmio, OBJECT(dev), &riscv_imsic_ops, > + imsic, TYPE_RISCV_IMSIC, > + IMSIC_MMIO_SIZE(imsic->num_pages)); > + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &imsic->mmio); > + } > > /* Claim the CPU interrupt to be triggered by this IMSIC */ > if (riscv_cpu_claim_interrupts(rcpu, > @@ -432,7 +435,10 @@ DeviceState *riscv_imsic_create(hwaddr addr, uint32_t hartid, bool mmode, > qdev_prop_set_uint32(dev, "num-irqs", num_ids + 1); > > sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); > - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); > + > + if (!kvm_irqchip_in_kernel()) { > + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); > + } > > for (i = 0; i < num_pages; i++) { > if (!i) {