From: LIU Zhiwei <baxiantai@gmail.com>
To: "Christoph Müllner" <christoph.muellner@vrull.eu>
Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
Palmer Dabbelt <palmer@dabbelt.com>,
Richard Henderson <richard.henderson@linaro.org>,
Zhiwei Liu <zhiwei_liu@linux.alibaba.com>,
Weiwei Li <liweiwei@iscas.ac.cn>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: Re: [PATCH 6/9] target/riscv/cpu: Share RISCVCPUConfig with disassembler
Date: Mon, 12 Jun 2023 18:01:28 +0800 [thread overview]
Message-ID: <18954fce-c08d-66f0-fe32-b6bdd4ac1892@gmail.com> (raw)
In-Reply-To: <CAEg0e7iShmcrvqXJkfy+wv+v4e2y=S4go52aTs8cZ_+Lb6rvwg@mail.gmail.com>
On 2023/6/12 17:47, Christoph Müllner wrote:
> On Mon, Jun 12, 2023 at 8:25 AM LIU Zhiwei <baxiantai@gmail.com> wrote:
>>
>> On 2023/5/30 21:18, Christoph Muellner wrote:
>>> From: Christoph Müllner <christoph.muellner@vrull.eu>
>>>
>>> The disassembler needs the available extensions in order
>>> to properly decode instructions in case of overlapping
>>> encodings (e.g. for vendor extensions).
>>>
>>> Let's use the field 'disassemble_info::private_data' to store
>>> our RISCVCPUConfig pointer.
>>>
>>> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
>>> ---
>>> target/riscv/cpu.c | 3 +++
>>> 1 file changed, 3 insertions(+)
>>>
>>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>>> index 5b7818dbd1..6f0cd9a0bb 100644
>>> --- a/target/riscv/cpu.c
>>> +++ b/target/riscv/cpu.c
>>> @@ -819,6 +819,9 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
>>> {
>>> RISCVCPU *cpu = RISCV_CPU(s);
>>> CPURISCVState *env = &cpu->env;
>>> + RISCVCPUConfig *cfg = &cpu->cfg;
>>> +
>>> + info->private_data = cfg;
>> I don't know if this field will be overridden by the binutils. Can we
>> extend the struct disassemble_info, and add some fields like supporting
>> for Capstone?
>
> Initially I wanted to add a new field, but then I noticed that the field
> 'disassemble_info::private_data' is used for a similar purpose by
> disas/cris.c, disas/m68k.c, and dias/xtensa.c.
> So I decided to not add yet another field, which only serves one architecture.
I think you can CC these arch maintainers to see if it need some
specially process before using the private_data.
>
> But if that's the preferred way, then I can change.
I prefer this way, but not insist on if it really works using the
private_data.
Zhiwei
>
> Thanks
> Christoph
>
>> Zhiwei
>>
>>> switch (env->xl) {
>>> case MXL_RV32:
next prev parent reply other threads:[~2023-06-12 10:02 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-30 13:18 [PATCH 0/9] disas/riscv: Add vendor extension support Christoph Muellner
2023-05-30 13:18 ` [PATCH 1/9] target/riscv: Use xl instead of mxl for disassemble Christoph Muellner
2023-05-30 13:18 ` [PATCH 2/9] target/riscv: Factor out RISCVCPUConfig from cpu.h Christoph Muellner
2023-06-12 3:21 ` Alistair Francis
2023-06-12 6:40 ` LIU Zhiwei
2023-05-30 13:18 ` [PATCH 3/9] disas/riscv: Move types/constants to new header file Christoph Muellner
2023-06-09 2:04 ` LIU Zhiwei
2023-06-12 3:22 ` Alistair Francis
2023-05-30 13:18 ` [PATCH 4/9] disas/riscv: Make rv_op_illegal a shared enum value Christoph Muellner
2023-06-12 3:24 ` Alistair Francis
2023-06-12 6:48 ` LIU Zhiwei
2023-05-30 13:18 ` [PATCH 5/9] disas/riscv: Encapsulate opcode_data into decode Christoph Muellner
2023-06-12 3:26 ` Alistair Francis
2023-05-30 13:18 ` [PATCH 6/9] target/riscv/cpu: Share RISCVCPUConfig with disassembler Christoph Muellner
2023-06-12 3:34 ` Alistair Francis
2023-06-12 6:25 ` LIU Zhiwei
2023-06-12 9:47 ` Christoph Müllner
2023-06-12 10:01 ` LIU Zhiwei [this message]
2023-06-12 10:04 ` Christoph Müllner
2023-06-12 11:56 ` LIU Zhiwei
2023-05-30 13:18 ` [PATCH 7/9] disas/riscv: Provide infrastructure for vendor extensions Christoph Muellner
2023-06-08 13:04 ` LIU Zhiwei
2023-06-12 11:11 ` Christoph Müllner
2023-06-12 3:37 ` Alistair Francis
2023-05-30 13:18 ` [PATCH 8/9] disas/riscv: Add support for XVentanaCondOps Christoph Muellner
2023-06-12 3:38 ` Alistair Francis
2023-05-30 13:18 ` [PATCH 9/9] disas/riscv: Add support for XThead* instructions Christoph Muellner
2023-06-12 3:40 ` Alistair Francis
2023-06-06 17:38 ` [PATCH 0/9] disas/riscv: Add vendor extension support Daniel Henrique Barboza
2023-06-12 11:17 ` Christoph Müllner
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=18954fce-c08d-66f0-fe32-b6bdd4ac1892@gmail.com \
--to=baxiantai@gmail.com \
--cc=alistair.francis@wdc.com \
--cc=bin.meng@windriver.com \
--cc=christoph.muellner@vrull.eu \
--cc=dbarboza@ventanamicro.com \
--cc=liweiwei@iscas.ac.cn \
--cc=palmer@dabbelt.com \
--cc=philipp.tomsich@vrull.eu \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=richard.henderson@linaro.org \
--cc=zhiwei_liu@linux.alibaba.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).