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[176.184.30.254]) by smtp.gmail.com with ESMTPSA id v7-20020a05600c214700b003f4f89bc48dsm5647135wml.15.2023.05.25.05.06.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 25 May 2023 05:06:59 -0700 (PDT) Message-ID: <1f33d65c-39a2-ceff-56dc-1982499066c6@linaro.org> Date: Thu, 25 May 2023 14:06:58 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH v4 2/3] hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b. Content-Language: en-US To: Tommy Wu , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: alistair.francis@wdc.com, palmer@dabbelt.com, bin.meng@windriver.com, jim.shu@sifive.com, frank.chang@sifive.com, thuth@redhat.com, liweiwei@iscas.ac.cn References: <20230523084910.304679-1-tommy.wu@sifive.com> <20230523084910.304679-3-tommy.wu@sifive.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230523084910.304679-3-tommy.wu@sifive.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.091, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On 23/5/23 10:49, Tommy Wu wrote: > Create the AON device when we realize the sifive_e machine. > This patch only implemented the functionality of the watchdog timer, > not all the functionality of the AON device. > > Signed-off-by: Tommy Wu > Reviewed-by: Frank Chang > --- > hw/riscv/Kconfig | 1 + > hw/riscv/sifive_e.c | 13 +++++++++++-- > include/hw/riscv/sifive_e.h | 8 +++++--- > 3 files changed, 17 insertions(+), 5 deletions(-) > diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h > index b824a79e2d..a094b47e0b 100644 > --- a/include/hw/riscv/sifive_e.h > +++ b/include/hw/riscv/sifive_e.h > @@ -35,6 +35,7 @@ typedef struct SiFiveESoCState { > /*< public >*/ > RISCVHartArrayState cpus; > DeviceState *plic; > + DeviceState *aon; Preferably allocate the device state in the SoC, similar to gpio: SiFiveEAONState aon; > SIFIVEGPIOState gpio; > MemoryRegion xip_mem; > MemoryRegion mask_rom; > @@ -76,9 +77,10 @@ enum { > }; >