From: Weiwei Li <liweiwei@iscas.ac.cn>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com,
bin.meng@windriver.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, wangjunqiang@iscas.ac.cn,
lazyparser@gmail.com, Weiwei Li <liweiwei@iscas.ac.cn>,
Richard Henderson <richard.henderson@linaro.org>
Subject: [PATCH v3 2/7] target/riscv: Introduce cur_insn_len into DisasContext
Date: Fri, 26 May 2023 15:21:19 +0800 [thread overview]
Message-ID: <20230526072124.298466-3-liweiwei@iscas.ac.cn> (raw)
In-Reply-To: <20230526072124.298466-1-liweiwei@iscas.ac.cn>
Use cur_insn_len to store the length of the current instruction to
prepare for PC-relative translation.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/translate.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 1b93de66ab..9feb0a4890 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -59,6 +59,7 @@ typedef struct DisasContext {
DisasContextBase base;
/* pc_succ_insn points to the instruction following base.pc_next */
target_ulong pc_succ_insn;
+ target_ulong cur_insn_len;
target_ulong priv_ver;
RISCVMXL misa_mxl_max;
RISCVMXL xl;
@@ -1114,8 +1115,9 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
};
ctx->virt_inst_excp = false;
+ ctx->cur_insn_len = insn_len(opcode);
/* Check for compressed insn */
- if (insn_len(opcode) == 2) {
+ if (ctx->cur_insn_len == 2) {
ctx->opcode = opcode;
ctx->pc_succ_insn = ctx->base.pc_next + 2;
/*
--
2.25.1
next prev parent reply other threads:[~2023-05-26 7:24 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-26 7:21 [PATCH v3 0/7] target/riscv: Add support for PC-relative translation Weiwei Li
2023-05-26 7:21 ` [PATCH v3 1/7] target/riscv: Fix target address to update badaddr Weiwei Li
2023-05-26 7:21 ` Weiwei Li [this message]
2023-05-26 7:21 ` [PATCH v3 3/7] target/riscv: Change gen_goto_tb to work on displacements Weiwei Li
2023-05-26 7:21 ` [PATCH v3 4/7] target/riscv: Change gen_set_pc_imm to gen_update_pc Weiwei Li
2023-05-26 7:21 ` [PATCH v3 5/7] target/riscv: Use true diff for gen_pc_plus_diff Weiwei Li
2023-05-26 7:21 ` [PATCH v3 6/7] target/riscv: Enable PC-relative translation Weiwei Li
2023-05-26 7:21 ` [PATCH v3 7/7] target/riscv: Remove pc_succ_insn from DisasContext Weiwei Li
2023-06-01 5:20 ` [PATCH v3 0/7] target/riscv: Add support for PC-relative translation Alistair Francis
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