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[200.162.225.121]) by smtp.gmail.com with ESMTPSA id j3-20020a056870a48300b0019fa8728b05sm342214oal.39.2023.05.30.12.47.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 12:47:15 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 14/16] target/riscv: adapt 'riscv_isa_string' for KVM Date: Tue, 30 May 2023 16:46:21 -0300 Message-Id: <20230530194623.272652-15-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230530194623.272652-1-dbarboza@ventanamicro.com> References: <20230530194623.272652-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::36; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org KVM is not using the same attributes as TCG, i.e. it doesn't use isa_edata_arr[]. Add a new kvm_riscv_isa_string_ext() helper that does basically the same thing, but using KVM internals instead. The decision to add this helper target/riscv/kvm.c is to foster the separation between KVM and TCG logic, while still using riscv_isa_string_ext() from target/riscv/cpu.c to retrieve the string to not overcomplicate things. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 5 +++++ target/riscv/kvm.c | 19 +++++++++++++++++++ target/riscv/kvm_riscv.h | 2 ++ 3 files changed, 26 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3c348049a3..ec1d0c621a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1956,6 +1956,11 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, char *new = *isa_str; int i; + if (riscv_running_KVM()) { + kvm_riscv_isa_string_ext(cpu, isa_str, max_str_len); + return; + } + for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { if (cpu->env.priv_ver >= isa_edata_arr[i].min_version && isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index b4193a10d8..675e18df3b 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -320,6 +320,25 @@ static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) } } +void kvm_riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, + int max_str_len) +{ + char *old = *isa_str; + char *new = *isa_str; + int i; + + for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { + RISCVCPUMultiExtConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; + if (kvm_cpu_cfg_get(cpu, multi_ext_cfg)) { + new = g_strconcat(old, "_", multi_ext_cfg->name, NULL); + g_free(old); + old = new; + } + } + + *isa_str = new; +} + static int kvm_riscv_get_regs_core(CPUState *cs) { int ret = 0; diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h index e3ba935808..1a12efa8db 100644 --- a/target/riscv/kvm_riscv.h +++ b/target/riscv/kvm_riscv.h @@ -20,6 +20,8 @@ #define QEMU_KVM_RISCV_H void kvm_riscv_init_user_properties(Object *cpu_obj); +void kvm_riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, + int max_str_len); void kvm_riscv_reset_vcpu(RISCVCPU *cpu); void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level); -- 2.40.1