From: Weiwei Li <liweiwei@iscas.ac.cn>
To: Tommy Wu <tommy.wu@sifive.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: liweiwei@iscas.ac.cn, frank.chang@sifive.com,
alistair.francis@wdc.com, apatel@ventanamicro.com,
palmer@rivosinc.com, dbarboza@ventanamicro.com,
bin.meng@windriver.com, zhiwei_liu@linux.alibaba.com
Subject: Re: [PATCH 1/2] target/riscv: Add a function to refresh the dynamic CSRs xml.
Date: Tue, 23 May 2023 22:37:37 +0800 [thread overview]
Message-ID: <5d3558a0-8b7f-8b84-a4e0-a6f4404a56b6@iscas.ac.cn> (raw)
In-Reply-To: <20230523114454.717708-2-tommy.wu@sifive.com>
On 2023/5/23 19:44, Tommy Wu wrote:
> When we change the cpu extension state after the cpu is
> realized, we cannot print the value of some CSRs in the remote
> gdb debugger. The root cause is that the dynamic CSR xml is
> generated when the cpu is realized.
>
> This patch add a function to refresh the dynamic CSR xml after
> the cpu is realized.
>
> Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/cpu.h | 2 ++
> target/riscv/gdbstub.c | 12 ++++++++++++
> 2 files changed, 14 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index de7e43126a..dc8e592275 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -494,6 +494,7 @@ struct ArchCPU {
> CPUNegativeOffsetState neg;
> CPURISCVState env;
>
> + int dyn_csr_base_reg;
dyn_csr_base_reg seems have no additional effect on the function.
And It remains unmodified in following riscv_refresh_dynamic_csr_xml().
Regards,
Weiwei Li
> char *dyn_csr_xml;
> char *dyn_vreg_xml;
>
> @@ -781,6 +782,7 @@ void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
> void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
>
> void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
> +void riscv_refresh_dynamic_csr_xml(CPUState *cs);
>
> uint8_t satp_mode_max_from_map(uint32_t map);
> const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index 524bede865..9e97ee2c35 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -230,6 +230,8 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg)
> bitsize = 64;
> }
>
> + cpu->dyn_csr_base_reg = base_reg;
> +
> g_string_printf(s, "<?xml version=\"1.0\"?>");
> g_string_append_printf(s, "<!DOCTYPE feature SYSTEM \"gdb-target.dtd\">");
> g_string_append_printf(s, "<feature name=\"org.gnu.gdb.riscv.csr\">");
> @@ -349,3 +351,13 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
> "riscv-csr.xml", 0);
> }
> }
> +
> +void riscv_refresh_dynamic_csr_xml(CPUState *cs)
> +{
> + RISCVCPU *cpu = RISCV_CPU(cs);
> + if (!cpu->dyn_csr_xml) {
> + g_assert_not_reached();
> + }
> + g_free(cpu->dyn_csr_xml);
> + riscv_gen_dynamic_csr_xml(cs, cpu->dyn_csr_base_reg);
> +}
next prev parent reply other threads:[~2023-05-23 14:38 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-23 11:44 [PATCH 0/2] Refresh the dynamic CSR xml after updating the state of the cpu Tommy Wu
2023-05-23 11:44 ` [PATCH 1/2] target/riscv: Add a function to refresh the dynamic CSRs xml Tommy Wu
2023-05-23 14:37 ` Weiwei Li [this message]
2023-05-24 1:59 ` Tommy Wu
2023-05-24 2:10 ` Weiwei Li
2023-05-24 5:35 ` Tommy Wu
2023-05-24 6:18 ` Weiwei Li
2023-05-25 2:33 ` Alistair Francis
2023-06-09 8:37 ` Tommy Wu
2023-06-12 2:52 ` Alistair Francis
2023-05-23 11:44 ` [PATCH 2/2] hw/intc: riscv_imsic: Refresh the CSRs xml after updating the state of the cpu Tommy Wu
2023-05-23 14:43 ` Weiwei Li
2023-05-24 1:51 ` Tommy Wu
2023-05-24 2:34 ` Weiwei Li
2023-05-24 5:46 ` Tommy Wu
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