[PATCH v3 0/2] Support for print to log vector extension registers

[PATCH v3 0/2] Support for print to log vector extension registers

[Ivan Klokov]

The patch added an ability to include VPU registers in the 'cpu' logging.
---
v3:
   - split of the patch into two parts: general and RISC-V specific
---

Ivan Klokov (2):
  util/log: Add vector registers to log
  target/riscv: Add RVV registers to log

 accel/tcg/cpu-exec.c  |  3 +++
 include/hw/core/cpu.h |  2 ++
 include/qemu/log.h    |  1 +
 target/riscv/cpu.c    | 56 ++++++++++++++++++++++++++++++++++++++++++-
 util/log.c            |  2 ++
 5 files changed, 63 insertions(+), 1 deletion(-)

-- 
2.34.1

[PATCH v3 1/2] util/log: Add vector registers to log

[Ivan Klokov]

Added QEMU option 'vpu' to log vector extension registers such as gpr\fpu.

Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>
---
 accel/tcg/cpu-exec.c  | 3 +++
 include/hw/core/cpu.h | 2 ++
 include/qemu/log.h    | 1 +
 util/log.c            | 2 ++
 4 files changed, 8 insertions(+)

diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 56aaf58b9d..0dca69fccb 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -319,6 +319,9 @@ static void log_cpu_exec(target_ulong pc, CPUState *cpu,
 #if defined(TARGET_I386)
                 flags |= CPU_DUMP_CCOP;
 #endif
+                if (qemu_loglevel_mask(CPU_LOG_TB_VPU)) {
+                    flags |= CPU_DUMP_VPU;
+                }
                 cpu_dump_state(cpu, logfile, flags);
                 qemu_log_unlock(logfile);
             }
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 75689bff02..7c9d25ff45 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -545,11 +545,13 @@ GuestPanicInformation *cpu_get_crash_info(CPUState *cpu);
  * @CPU_DUMP_CODE:
  * @CPU_DUMP_FPU: dump FPU register state, not just integer
  * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state
+ * @CPU_DUMP_VPU: dump VPU registers
  */
 enum CPUDumpFlags {
     CPU_DUMP_CODE = 0x00010000,
     CPU_DUMP_FPU  = 0x00020000,
     CPU_DUMP_CCOP = 0x00040000,
+    CPU_DUMP_VPU  = 0x00080000,
 };
 
 /**
diff --git a/include/qemu/log.h b/include/qemu/log.h
index c5643d8dd5..df59bfabcd 100644
--- a/include/qemu/log.h
+++ b/include/qemu/log.h
@@ -35,6 +35,7 @@ bool qemu_log_separate(void);
 /* LOG_STRACE is used for user-mode strace logging. */
 #define LOG_STRACE         (1 << 19)
 #define LOG_PER_THREAD     (1 << 20)
+#define CPU_LOG_TB_VPU     (1 << 21)
 
 /* Lock/unlock output. */
 
diff --git a/util/log.c b/util/log.c
index 7837ff9917..93dccee7b8 100644
--- a/util/log.c
+++ b/util/log.c
@@ -495,6 +495,8 @@ const QEMULogItem qemu_log_items[] = {
       "log every user-mode syscall, its input, and its result" },
     { LOG_PER_THREAD, "tid",
       "open a separate log file per thread; filename must contain '%d'" },
+    { CPU_LOG_TB_VPU, "vpu",
+      "include VPU registers in the 'cpu' logging" },
     { 0, NULL, NULL },
 };
 
-- 
2.34.1

[PATCH v3 2/2] target/riscv: Add RVV registers to log

[Ivan Klokov]

Print RvV extesion register to log if VPU option is enabled.

Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>
---
 target/riscv/cpu.c | 56 +++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 55 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5bc0005cc7..cfd063a5dc 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -172,6 +172,14 @@ const char * const riscv_fpr_regnames[] = {
   "f30/ft10", "f31/ft11"
 };
 
+const char * const riscv_rvv_regnames[] = {
+  "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",
+  "v7",  "v8",  "v9",  "v10", "v11", "v12", "v13",
+  "v14", "v15", "v16", "v17", "v18", "v19", "v20",
+  "v21", "v22", "v23", "v24", "v25", "v26", "v27",
+  "v28", "v29", "v30", "v31"
+};
+
 static const char * const riscv_excp_names[] = {
     "misaligned_fetch",
     "fault_fetch",
@@ -422,7 +430,8 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 {
     RISCVCPU *cpu = RISCV_CPU(cs);
     CPURISCVState *env = &cpu->env;
-    int i;
+    int i, j;
+    uint8_t *p;
 
 #if !defined(CONFIG_USER_ONLY)
     if (riscv_has_ext(env, RVH)) {
@@ -506,6 +515,51 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
             }
         }
     }
+    if (riscv_has_ext(env, RVV) && (flags & CPU_DUMP_VPU)) {
+        static const int dump_rvv_csrs[] = {
+                    CSR_VSTART,
+                    CSR_VXSAT,
+                    CSR_VXRM,
+                    CSR_VCSR,
+                    CSR_VL,
+                    CSR_VTYPE,
+                    CSR_VLENB,
+                };
+        for (int i = 0; i < ARRAY_SIZE(dump_rvv_csrs); ++i) {
+            int csrno = dump_rvv_csrs[i];
+            target_ulong val = 0;
+            RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
+
+            /*
+             * Rely on the smode, hmode, etc, predicates within csr.c
+             * to do the filtering of the registers that are present.
+             */
+            if (res == RISCV_EXCP_NONE) {
+                qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
+                             csr_ops[csrno].name, val);
+            }
+        }
+        uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
+
+/*
+ * From vector_helper.c
+ * Note that vector data is stored in host-endian 64-bit chunks,
+ * so addressing bytes needs a host-endian fixup.
+ */
+#if HOST_BIG_ENDIAN
+#define BYTE(x)   ((x) ^ 7)
+#else
+#define BYTE(x)   (x)
+#endif
+        for (i = 0; i < 32; i++) {
+            qemu_fprintf(f, " %-8s ", riscv_rvv_regnames[i]);
+            p = (uint8_t *)env->vreg;
+            for (j = vlenb - 1 ; j >= 0; j--) {
+                qemu_fprintf(f, "%02x", *(p + i * vlenb + BYTE(j)));
+            }
+            qemu_fprintf(f, "\n");
+        }
+    }
 }
 
 static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
-- 
2.34.1

Re: [PATCH v3 1/2] util/log: Add vector registers to log

[Alistair Francis]

On Mon, Apr 10, 2023 at 10:46 PM Ivan Klokov <ivan.klokov@syntacore.com> wrote:
>
> Added QEMU option 'vpu' to log vector extension registers such as gpr\fpu.
>
> Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  accel/tcg/cpu-exec.c  | 3 +++
>  include/hw/core/cpu.h | 2 ++
>  include/qemu/log.h    | 1 +
>  util/log.c            | 2 ++
>  4 files changed, 8 insertions(+)
>
> diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
> index 56aaf58b9d..0dca69fccb 100644
> --- a/accel/tcg/cpu-exec.c
> +++ b/accel/tcg/cpu-exec.c
> @@ -319,6 +319,9 @@ static void log_cpu_exec(target_ulong pc, CPUState *cpu,
>  #if defined(TARGET_I386)
>                  flags |= CPU_DUMP_CCOP;
>  #endif
> +                if (qemu_loglevel_mask(CPU_LOG_TB_VPU)) {
> +                    flags |= CPU_DUMP_VPU;
> +                }
>                  cpu_dump_state(cpu, logfile, flags);
>                  qemu_log_unlock(logfile);
>              }
> diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
> index 75689bff02..7c9d25ff45 100644
> --- a/include/hw/core/cpu.h
> +++ b/include/hw/core/cpu.h
> @@ -545,11 +545,13 @@ GuestPanicInformation *cpu_get_crash_info(CPUState *cpu);
>   * @CPU_DUMP_CODE:
>   * @CPU_DUMP_FPU: dump FPU register state, not just integer
>   * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state
> + * @CPU_DUMP_VPU: dump VPU registers
>   */
>  enum CPUDumpFlags {
>      CPU_DUMP_CODE = 0x00010000,
>      CPU_DUMP_FPU  = 0x00020000,
>      CPU_DUMP_CCOP = 0x00040000,
> +    CPU_DUMP_VPU  = 0x00080000,
>  };
>
>  /**
> diff --git a/include/qemu/log.h b/include/qemu/log.h
> index c5643d8dd5..df59bfabcd 100644
> --- a/include/qemu/log.h
> +++ b/include/qemu/log.h
> @@ -35,6 +35,7 @@ bool qemu_log_separate(void);
>  /* LOG_STRACE is used for user-mode strace logging. */
>  #define LOG_STRACE         (1 << 19)
>  #define LOG_PER_THREAD     (1 << 20)
> +#define CPU_LOG_TB_VPU     (1 << 21)
>
>  /* Lock/unlock output. */
>
> diff --git a/util/log.c b/util/log.c
> index 7837ff9917..93dccee7b8 100644
> --- a/util/log.c
> +++ b/util/log.c
> @@ -495,6 +495,8 @@ const QEMULogItem qemu_log_items[] = {
>        "log every user-mode syscall, its input, and its result" },
>      { LOG_PER_THREAD, "tid",
>        "open a separate log file per thread; filename must contain '%d'" },
> +    { CPU_LOG_TB_VPU, "vpu",
> +      "include VPU registers in the 'cpu' logging" },
>      { 0, NULL, NULL },
>  };
>
> --
> 2.34.1
>
>

Re: [PATCH v3 2/2] target/riscv: Add RVV registers to log

[Alistair Francis]

On Mon, Apr 10, 2023 at 10:47 PM Ivan Klokov <ivan.klokov@syntacore.com> wrote:
>
> Print RvV extesion register to log if VPU option is enabled.
>
> Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c | 56 +++++++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 55 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 5bc0005cc7..cfd063a5dc 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -172,6 +172,14 @@ const char * const riscv_fpr_regnames[] = {
>    "f30/ft10", "f31/ft11"
>  };
>
> +const char * const riscv_rvv_regnames[] = {
> +  "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",
> +  "v7",  "v8",  "v9",  "v10", "v11", "v12", "v13",
> +  "v14", "v15", "v16", "v17", "v18", "v19", "v20",
> +  "v21", "v22", "v23", "v24", "v25", "v26", "v27",
> +  "v28", "v29", "v30", "v31"
> +};
> +
>  static const char * const riscv_excp_names[] = {
>      "misaligned_fetch",
>      "fault_fetch",
> @@ -422,7 +430,8 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
>  {
>      RISCVCPU *cpu = RISCV_CPU(cs);
>      CPURISCVState *env = &cpu->env;
> -    int i;
> +    int i, j;
> +    uint8_t *p;
>
>  #if !defined(CONFIG_USER_ONLY)
>      if (riscv_has_ext(env, RVH)) {
> @@ -506,6 +515,51 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
>              }
>          }
>      }
> +    if (riscv_has_ext(env, RVV) && (flags & CPU_DUMP_VPU)) {
> +        static const int dump_rvv_csrs[] = {
> +                    CSR_VSTART,
> +                    CSR_VXSAT,
> +                    CSR_VXRM,
> +                    CSR_VCSR,
> +                    CSR_VL,
> +                    CSR_VTYPE,
> +                    CSR_VLENB,
> +                };
> +        for (int i = 0; i < ARRAY_SIZE(dump_rvv_csrs); ++i) {
> +            int csrno = dump_rvv_csrs[i];
> +            target_ulong val = 0;
> +            RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
> +
> +            /*
> +             * Rely on the smode, hmode, etc, predicates within csr.c
> +             * to do the filtering of the registers that are present.
> +             */
> +            if (res == RISCV_EXCP_NONE) {
> +                qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
> +                             csr_ops[csrno].name, val);
> +            }
> +        }
> +        uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
> +
> +/*
> + * From vector_helper.c
> + * Note that vector data is stored in host-endian 64-bit chunks,
> + * so addressing bytes needs a host-endian fixup.
> + */
> +#if HOST_BIG_ENDIAN
> +#define BYTE(x)   ((x) ^ 7)
> +#else
> +#define BYTE(x)   (x)
> +#endif
> +        for (i = 0; i < 32; i++) {
> +            qemu_fprintf(f, " %-8s ", riscv_rvv_regnames[i]);
> +            p = (uint8_t *)env->vreg;
> +            for (j = vlenb - 1 ; j >= 0; j--) {
> +                qemu_fprintf(f, "%02x", *(p + i * vlenb + BYTE(j)));
> +            }
> +            qemu_fprintf(f, "\n");
> +        }
> +    }
>  }
>
>  static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
> --
> 2.34.1
>
>

Re: [PATCH v3 0/2] Support for print to log vector extension registers

[Alistair Francis]

On Mon, Apr 10, 2023 at 10:46 PM Ivan Klokov <ivan.klokov@syntacore.com> wrote:
>
> The patch added an ability to include VPU registers in the 'cpu' logging.
> ---
> v3:
>    - split of the patch into two parts: general and RISC-V specific
> ---
>
> Ivan Klokov (2):
>   util/log: Add vector registers to log
>   target/riscv: Add RVV registers to log

I'm going to go ahead and merge this

Applied to riscv-to-apply.next

Alistair

>
>  accel/tcg/cpu-exec.c  |  3 +++
>  include/hw/core/cpu.h |  2 ++
>  include/qemu/log.h    |  1 +
>  target/riscv/cpu.c    | 56 ++++++++++++++++++++++++++++++++++++++++++-
>  util/log.c            |  2 ++
>  5 files changed, 63 insertions(+), 1 deletion(-)
>
> --
> 2.34.1
>
>

Re: [PATCH v3 2/2] target/riscv: Add RVV registers to log

[Alistair Francis]

On Mon, Apr 10, 2023 at 10:47 PM Ivan Klokov <ivan.klokov@syntacore.com> wrote:
>
> Print RvV extesion register to log if VPU option is enabled.
>
> Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>

I applied the first patch, unfortunately this one doesn't apply
anymore. Do you mind rebasing this on
https://github.com/alistair23/qemu/tree/riscv-to-apply.next

Alistair

> ---
>  target/riscv/cpu.c | 56 +++++++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 55 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 5bc0005cc7..cfd063a5dc 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -172,6 +172,14 @@ const char * const riscv_fpr_regnames[] = {
>    "f30/ft10", "f31/ft11"
>  };
>
> +const char * const riscv_rvv_regnames[] = {
> +  "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",
> +  "v7",  "v8",  "v9",  "v10", "v11", "v12", "v13",
> +  "v14", "v15", "v16", "v17", "v18", "v19", "v20",
> +  "v21", "v22", "v23", "v24", "v25", "v26", "v27",
> +  "v28", "v29", "v30", "v31"
> +};
> +
>  static const char * const riscv_excp_names[] = {
>      "misaligned_fetch",
>      "fault_fetch",
> @@ -422,7 +430,8 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
>  {
>      RISCVCPU *cpu = RISCV_CPU(cs);
>      CPURISCVState *env = &cpu->env;
> -    int i;
> +    int i, j;
> +    uint8_t *p;
>
>  #if !defined(CONFIG_USER_ONLY)
>      if (riscv_has_ext(env, RVH)) {
> @@ -506,6 +515,51 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
>              }
>          }
>      }
> +    if (riscv_has_ext(env, RVV) && (flags & CPU_DUMP_VPU)) {
> +        static const int dump_rvv_csrs[] = {
> +                    CSR_VSTART,
> +                    CSR_VXSAT,
> +                    CSR_VXRM,
> +                    CSR_VCSR,
> +                    CSR_VL,
> +                    CSR_VTYPE,
> +                    CSR_VLENB,
> +                };
> +        for (int i = 0; i < ARRAY_SIZE(dump_rvv_csrs); ++i) {
> +            int csrno = dump_rvv_csrs[i];
> +            target_ulong val = 0;
> +            RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
> +
> +            /*
> +             * Rely on the smode, hmode, etc, predicates within csr.c
> +             * to do the filtering of the registers that are present.
> +             */
> +            if (res == RISCV_EXCP_NONE) {
> +                qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
> +                             csr_ops[csrno].name, val);
> +            }
> +        }
> +        uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
> +
> +/*
> + * From vector_helper.c
> + * Note that vector data is stored in host-endian 64-bit chunks,
> + * so addressing bytes needs a host-endian fixup.
> + */
> +#if HOST_BIG_ENDIAN
> +#define BYTE(x)   ((x) ^ 7)
> +#else
> +#define BYTE(x)   (x)
> +#endif
> +        for (i = 0; i < 32; i++) {
> +            qemu_fprintf(f, " %-8s ", riscv_rvv_regnames[i]);
> +            p = (uint8_t *)env->vreg;
> +            for (j = vlenb - 1 ; j >= 0; j--) {
> +                qemu_fprintf(f, "%02x", *(p + i * vlenb + BYTE(j)));
> +            }
> +            qemu_fprintf(f, "\n");
> +        }
> +    }
>  }
>
>  static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
> --
> 2.34.1
>
>

Re: [PATCH v3 2/2] target/riscv: Add RVV registers to log

[Philippe Mathieu-Daudé]

On 2/6/23 05:43, Alistair Francis wrote:
> On Mon, Apr 10, 2023 at 10:47 PM Ivan Klokov <ivan.klokov@syntacore.com> wrote:
>>
>> Print RvV extesion register to log if VPU option is enabled.
>>
>> Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>
> 
> I applied the first patch, unfortunately this one doesn't apply
> anymore. Do you mind rebasing this on
> https://github.com/alistair23/qemu/tree/riscv-to-apply.next
> 
> Alistair
> 
>> ---
>>   target/riscv/cpu.c | 56 +++++++++++++++++++++++++++++++++++++++++++++-
>>   1 file changed, 55 insertions(+), 1 deletion(-)
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index 5bc0005cc7..cfd063a5dc 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -172,6 +172,14 @@ const char * const riscv_fpr_regnames[] = {
>>     "f30/ft10", "f31/ft11"
>>   };
>>
>> +const char * const riscv_rvv_regnames[] = {
>> +  "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",
>> +  "v7",  "v8",  "v9",  "v10", "v11", "v12", "v13",
>> +  "v14", "v15", "v16", "v17", "v18", "v19", "v20",
>> +  "v21", "v22", "v23", "v24", "v25", "v26", "v27",
>> +  "v28", "v29", "v30", "v31"
>> +};
>> +
>>   static const char * const riscv_excp_names[] = {
>>       "misaligned_fetch",
>>       "fault_fetch",
>> @@ -422,7 +430,8 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
>>   {
>>       RISCVCPU *cpu = RISCV_CPU(cs);
>>       CPURISCVState *env = &cpu->env;
>> -    int i;
>> +    int i, j;
>> +    uint8_t *p;
>>
>>   #if !defined(CONFIG_USER_ONLY)
>>       if (riscv_has_ext(env, RVH)) {
>> @@ -506,6 +515,51 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
>>               }
>>           }
>>       }
>> +    if (riscv_has_ext(env, RVV) && (flags & CPU_DUMP_VPU)) {
>> +        static const int dump_rvv_csrs[] = {
>> +                    CSR_VSTART,
>> +                    CSR_VXSAT,
>> +                    CSR_VXRM,
>> +                    CSR_VCSR,
>> +                    CSR_VL,
>> +                    CSR_VTYPE,
>> +                    CSR_VLENB,
>> +                };
>> +        for (int i = 0; i < ARRAY_SIZE(dump_rvv_csrs); ++i) {
>> +            int csrno = dump_rvv_csrs[i];
>> +            target_ulong val = 0;
>> +            RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
>> +
>> +            /*
>> +             * Rely on the smode, hmode, etc, predicates within csr.c
>> +             * to do the filtering of the registers that are present.
>> +             */
>> +            if (res == RISCV_EXCP_NONE) {
>> +                qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
>> +                             csr_ops[csrno].name, val);
>> +            }
>> +        }
>> +        uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
>> +
>> +/*
>> + * From vector_helper.c
>> + * Note that vector data is stored in host-endian 64-bit chunks,
>> + * so addressing bytes needs a host-endian fixup.

Hmm we should have a ld/st API helper for that. Maybe something like:

   uint64_t val = ldq_he_p(env->vreg[i * vlenb]);

>> + */
>> +#if HOST_BIG_ENDIAN
>> +#define BYTE(x)   ((x) ^ 7)
>> +#else
>> +#define BYTE(x)   (x)
>> +#endif
>> +        for (i = 0; i < 32; i++) {
>> +            qemu_fprintf(f, " %-8s ", riscv_rvv_regnames[i]);
>> +            p = (uint8_t *)env->vreg;
>> +            for (j = vlenb - 1 ; j >= 0; j--) {
>> +                qemu_fprintf(f, "%02x", *(p + i * vlenb + BYTE(j)));
>> +            }
>> +            qemu_fprintf(f, "\n");
>> +        }
>> +    }
>>   }
>>
>>   static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
>> --
>> 2.34.1
>>
>>