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Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH v3 2/2] target/riscv: Add RVV registers to log Content-Language: en-US To: Alistair Francis , Ivan Klokov Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, richard.henderson@linaro.org, pbonzini@redhat.com, eduardo@habkost.net, marcel.apfelbaum@gmail.com, wangyanan55@huawei.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com References: <20230410124451.15929-1-ivan.klokov@syntacore.com> <20230410124451.15929-3-ivan.klokov@syntacore.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On 2/6/23 05:43, Alistair Francis wrote: > On Mon, Apr 10, 2023 at 10:47 PM Ivan Klokov wrote: >> >> Print RvV extesion register to log if VPU option is enabled. >> >> Signed-off-by: Ivan Klokov > > I applied the first patch, unfortunately this one doesn't apply > anymore. Do you mind rebasing this on > https://github.com/alistair23/qemu/tree/riscv-to-apply.next > > Alistair > >> --- >> target/riscv/cpu.c | 56 +++++++++++++++++++++++++++++++++++++++++++++- >> 1 file changed, 55 insertions(+), 1 deletion(-) >> >> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c >> index 5bc0005cc7..cfd063a5dc 100644 >> --- a/target/riscv/cpu.c >> +++ b/target/riscv/cpu.c >> @@ -172,6 +172,14 @@ const char * const riscv_fpr_regnames[] = { >> "f30/ft10", "f31/ft11" >> }; >> >> +const char * const riscv_rvv_regnames[] = { >> + "v0", "v1", "v2", "v3", "v4", "v5", "v6", >> + "v7", "v8", "v9", "v10", "v11", "v12", "v13", >> + "v14", "v15", "v16", "v17", "v18", "v19", "v20", >> + "v21", "v22", "v23", "v24", "v25", "v26", "v27", >> + "v28", "v29", "v30", "v31" >> +}; >> + >> static const char * const riscv_excp_names[] = { >> "misaligned_fetch", >> "fault_fetch", >> @@ -422,7 +430,8 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) >> { >> RISCVCPU *cpu = RISCV_CPU(cs); >> CPURISCVState *env = &cpu->env; >> - int i; >> + int i, j; >> + uint8_t *p; >> >> #if !defined(CONFIG_USER_ONLY) >> if (riscv_has_ext(env, RVH)) { >> @@ -506,6 +515,51 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) >> } >> } >> } >> + if (riscv_has_ext(env, RVV) && (flags & CPU_DUMP_VPU)) { >> + static const int dump_rvv_csrs[] = { >> + CSR_VSTART, >> + CSR_VXSAT, >> + CSR_VXRM, >> + CSR_VCSR, >> + CSR_VL, >> + CSR_VTYPE, >> + CSR_VLENB, >> + }; >> + for (int i = 0; i < ARRAY_SIZE(dump_rvv_csrs); ++i) { >> + int csrno = dump_rvv_csrs[i]; >> + target_ulong val = 0; >> + RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); >> + >> + /* >> + * Rely on the smode, hmode, etc, predicates within csr.c >> + * to do the filtering of the registers that are present. >> + */ >> + if (res == RISCV_EXCP_NONE) { >> + qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", >> + csr_ops[csrno].name, val); >> + } >> + } >> + uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3; >> + >> +/* >> + * From vector_helper.c >> + * Note that vector data is stored in host-endian 64-bit chunks, >> + * so addressing bytes needs a host-endian fixup. Hmm we should have a ld/st API helper for that. Maybe something like: uint64_t val = ldq_he_p(env->vreg[i * vlenb]); >> + */ >> +#if HOST_BIG_ENDIAN >> +#define BYTE(x) ((x) ^ 7) >> +#else >> +#define BYTE(x) (x) >> +#endif >> + for (i = 0; i < 32; i++) { >> + qemu_fprintf(f, " %-8s ", riscv_rvv_regnames[i]); >> + p = (uint8_t *)env->vreg; >> + for (j = vlenb - 1 ; j >= 0; j--) { >> + qemu_fprintf(f, "%02x", *(p + i * vlenb + BYTE(j))); >> + } >> + qemu_fprintf(f, "\n"); >> + } >> + } >> } >> >> static void riscv_cpu_set_pc(CPUState *cs, vaddr value) >> -- >> 2.34.1 >> >>