qemu-riscv.nongnu.org archive mirror

 messages from 2023-04-05 06:46:04 to 2023-04-10 12:45:34 UTC [more...]

[PATCH v3 0/2] Support for print to log vector extension registers
 2023-04-10 12:44 UTC  (3+ messages)
` [PATCH v3 1/2] util/log: Add vector registers to log
` [PATCH v3 2/2] target/riscv: Add RVV "

[PATCH 0/4] target/riscv: implement query-cpu-definitions
 2023-04-10 12:29 UTC  (5+ messages)
` [PATCH 1/4] target/riscv: add CPU QOM header
` [PATCH 2/4] target/riscv: add query-cpy-definitions support
` [PATCH 3/4] target/riscv: add 'static' attribute of query-cpu-definitions
` [PATCH 4/4] target/riscv: make generic cpus not static

[PATCH 0/2] target/riscv: Separate implicitly-enabled and explicitly-enabled extensions
 2023-04-10  3:35 UTC  (3+ messages)
` [PATCH 1/2] target/riscv: Add set_implicit_extensions_from_ext() function
` [PATCH 2/2] target/riscv: Add ext_z*_enabled for implicitly enabled extensions

[PATCH 0/7] target/riscv: Add support for PC-relative translation
 2023-04-09 10:53 UTC  (8+ messages)
` [PATCH 1/7] target/riscv: Fix target address to update badaddr
` [PATCH 2/7] target/riscv: Introduce cur_insn_len into DisasContext
` [PATCH 3/7] target/riscv: Change gen_goto_tb to work on displacements
` [PATCH 4/7] target/riscv: Change gen_set_pc_imm to gen_update_pc
` [PATCH 5/7] target/riscv: Use true diff for gen_pc_plus_diff
` [PATCH 6/7] target/riscv: Enable PC-relative translation
` [PATCH 7/7] target/riscv: Remove pc_succ_insn from DisasContext

[PATCH] target/riscv: Use check for relationship between Zdinx/Zhinx{min} and Zfinx
 2023-04-08 13:59 UTC 

[PATCH v2] target/riscv: Fix Guest Physical Address Translation
 2023-04-08 12:30 UTC  (2+ messages)

[PATCH 00/10] accel/kvm: Spring cleaning
 2023-04-08  4:29 UTC  (31+ messages)
` [PATCH 01/10] sysemu/kvm: Remove unused headers
` [PATCH 02/10] accel/kvm: Declare kvm_direct_msi_allowed in stubs
` [PATCH 03/10] hw/intc/arm_gic: Un-inline GIC*/ITS class_name() helpers
` [PATCH 04/10] hw/intc/arm_gic: Rename 'first_cpu' argument
` [PATCH 05/10] hw/arm/sbsa-ref: Include missing 'sysemu/kvm.h' header
` [PATCH 06/10] target/arm: Reduce QMP header pressure by not including 'kvm_arm.h'
` [PATCH 07/10] target/arm: Restrict KVM-specific fields from ArchCPU
` [PATCH 08/10] target/ppc: Restrict KVM-specific field "
` [RFC PATCH 09/10] target/riscv: Restrict KVM-specific fields "
` [PATCH 10/10] hw/s390x: Rename pv.c -> pv-kvm.c

[PATCH for-8.1 00/42] tcg: Simplify calls to load/store helpers
 2023-04-08  2:43 UTC  (44+ messages)
` [PATCH for-8.0] tcg/i386: Adjust assert in tcg_out_addi_ptr
` [PATCH 01/42] tcg: Replace if + tcg_abort with tcg_debug_assert
` [PATCH 02/42] tcg: Replace tcg_abort with g_assert_not_reached
` [PATCH 03/42] tcg: Split out tcg_out_ext8s
` [PATCH 04/42] tcg: Split out tcg_out_ext8u
` [PATCH 05/42] tcg: Split out tcg_out_ext16s
` [PATCH 06/42] tcg: Split out tcg_out_ext16u
` [PATCH 07/42] tcg: Split out tcg_out_ext32s
` [PATCH 08/42] tcg: Split out tcg_out_ext32u
` [PATCH 09/42] tcg: Split out tcg_out_exts_i32_i64
` [PATCH 10/42] tcg/loongarch64: Conditionalize tcg_out_exts_i32_i64
` [PATCH 11/42] tcg/mips: "
` [PATCH 12/42] tcg/riscv: "
` [PATCH 13/42] tcg: Split out tcg_out_extu_i32_i64
` [PATCH 14/42] tcg/i386: Conditionalize tcg_out_extu_i32_i64
` [PATCH 15/42] tcg: Split out tcg_out_extrl_i64_i32
` [PATCH 16/42] tcg: Introduce tcg_out_movext
` [PATCH 17/42] tcg: Introduce tcg_out_xchg
` [PATCH 18/42] tcg: Introduce tcg_out_movext2
` [PATCH 19/42] tcg: Clear TCGLabelQemuLdst on allocation
` [PATCH 20/42] tcg/i386: Use TCGType not bool is_64 in tcg_out_qemu_{ld, st}
` [PATCH 21/42] tcg/aarch64: Rename ext to d_type in tcg_out_qemu_ld
` [PATCH 22/42] tcg/aarch64: Pass TGType to tcg_out_qemu_st
` [PATCH 23/42] tcg/arm: Use TCGType not bool is_64 in tcg_out_qemu_{ld, st}
` [PATCH 24/42] tcg/i386: "
` [PATCH 25/42] tcg/ppc: "
` [PATCH 26/42] tcg/s390x: Pass TCGType to tcg_out_qemu_{ld,st}
` [PATCH 27/42] tcg/riscv: Require TCG_TARGET_REG_BITS == 64
` [PATCH 28/42] tcg/riscv: Expand arguments to tcg_out_qemu_{ld,st}
` [PATCH 29/42] tcg: Move TCGLabelQemuLdst to tcg.c
` [PATCH 30/42] tcg: Introduce tcg_out_ld_helper_args
` [PATCH 31/42] tcg: Introduce tcg_out_st_helper_args
` [PATCH 32/42] tcg/loongarch64: Simplify constraints on qemu_ld/st
` [PATCH 33/42] tcg/mips: Reorg tcg_out_tlb_load
` [PATCH 34/42] tcg/mips: Simplify constraints on qemu_ld/st
` [PATCH 35/42] tcg/ppc: Reorg tcg_out_tlb_read
` [PATCH 36/42] tcg/ppc: Adjust constraints on qemu_ld/st
` [PATCH 37/42] tcg/ppc: Remove unused constraints A, B, C, D
` [PATCH 38/42] tcg/riscv: Simplify constraints on qemu_ld/st
` [PATCH 39/42] tcg/s390x: Use ALGFR in constructing host address for qemu_ld/st
` [PATCH 40/42] tcg/s390x: Simplify constraints on qemu_ld/st
` [PATCH 41/42] tcg/sparc64: Drop is_64 test from tcg_out_qemu_ld data return
` [PATCH 42/42] tcg/sparc64: Pass TCGType to tcg_out_qemu_{ld,st}

[PATCH v12 00/10] support subsets of code size reduction extension
 2023-04-08  1:09 UTC  (9+ messages)
` [PATCH v12 02/10] target/riscv: add support for Zca extension

[PATCH v3 0/3] target/riscv: Fix mstatus.MPP related support
 2023-04-07 16:32 UTC  (6+ messages)
` [PATCH v3 1/3] target/riscv: Fix the mstatus.MPP value after executing MRET
` [PATCH v3 2/3] target/riscv: Use PRV_RESERVED instead of PRV_H
` [PATCH v3 3/3] target/riscv: Legalize MPP value in write_mstatus

[PATCH] target/riscv: Mask the implicitly enabled extensions in isa_string based on priv version
 2023-04-07 11:39 UTC  (3+ messages)

[PATCH v3 0/1] Fix max initrd size limit when put initrd to RAM
 2023-04-07  4:26 UTC  (5+ messages)
` [PATCH v3 1/1] hw/riscv: Fix max "
    `  "

[PATCH v2 0/2] target/riscv: Fix mstatus.MPP related support
 2023-04-07  1:24 UTC  (7+ messages)
` [PATCH v2 1/2] target/riscv: Fix the mstatus.MPP value after executing MRET
` [PATCH v2 2/2] target/riscv: Legalize MPP value in write_mstatus

[PATCH v4 00/20] remove MISA ext_N flags from cpu->cfg
 2023-04-06 18:03 UTC  (21+ messages)
` [PATCH v4 01/20] target/riscv: sync env->misa_ext* with cpu->cfg in realize()
` [PATCH v4 02/20] target/riscv: remove MISA properties from isa_edata_arr[]
` [PATCH v4 03/20] target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data
` [PATCH v4 04/20] target/riscv: introduce riscv_cpu_add_misa_properties()
` [PATCH v4 05/20] target/riscv: remove cpu->cfg.ext_a
` [PATCH v4 06/20] target/riscv: remove cpu->cfg.ext_c
` [PATCH v4 07/20] target/riscv: remove cpu->cfg.ext_d
` [PATCH v4 08/20] target/riscv: remove cpu->cfg.ext_f
` [PATCH v4 09/20] target/riscv: remove cpu->cfg.ext_i
` [PATCH v4 10/20] target/riscv: remove cpu->cfg.ext_e
` [PATCH v4 11/20] target/riscv: remove cpu->cfg.ext_m
` [PATCH v4 12/20] target/riscv: remove cpu->cfg.ext_s
` [PATCH v4 13/20] target/riscv: remove cpu->cfg.ext_u
` [PATCH v4 14/20] target/riscv: remove cpu->cfg.ext_h
` [PATCH v4 15/20] target/riscv: remove cpu->cfg.ext_j
` [PATCH v4 16/20] target/riscv: remove cpu->cfg.ext_v
` [PATCH v4 17/20] target/riscv: remove riscv_cpu_sync_misa_cfg()
` [PATCH v4 18/20] target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init()
` [PATCH v4 19/20] target/riscv: add RVG and remove cpu->cfg.ext_g
` [PATCH v4 20/20] target/riscv/cpu.c: redesign register_cpu_props()

[PATCH v4] target/riscv: fix H extension TVM trap
 2023-04-06 10:24 UTC  (3+ messages)
  `  "

[PATCH v5] target/riscv: fix H extension TVM trap
 2023-04-06 10:15 UTC 

[PATCH 0/2] target/riscv: Fix mstatus.MPP related support
 2023-04-06  3:55 UTC  (13+ messages)
` [PATCH 1/2] target/riscv: Fix the mstatus.MPP value after executing MRET
` [PATCH 2/2] target/riscv: Legalize MPP value in write_mstatus

[PATCH v6 00/25] target/riscv: MSTATUS_SUM + cleanups
 2023-04-06  2:35 UTC  (3+ messages)
` [PATCH v6 01/25] target/riscv: Extract virt enabled state from tb flags

[PATCH v6 0/9] target/riscv: rework CPU extensions validation
 2023-04-06  2:12 UTC  (17+ messages)
` [PATCH v6 1/9] target/riscv/cpu.c: add riscv_cpu_validate_v()
` [PATCH v6 2/9] target/riscv/cpu.c: remove set_vext_version()
` [PATCH v6 3/9] target/riscv/cpu.c: remove set_priv_version()
` [PATCH v6 4/9] target/riscv: add PRIV_VERSION_LATEST
` [PATCH v6 5/9] target/riscv/cpu.c: add priv_spec validate/disable_exts helpers
` [PATCH v6 6/9] target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl()
` [PATCH v6 7/9] target/riscv/cpu.c: validate extensions before riscv_timer_init()
` [PATCH v6 8/9] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()

[PATCH v4 0/1] hw/riscv: Add ACT related support
 2023-04-06  1:31 UTC  (6+ messages)
` [PATCH v4 1/1] hw/riscv: Add signature dump function for spike to run ACT tests

[PATCH v3 00/20] remove MISA ext_N flags from cpu->cfg,
 2023-04-06  0:32 UTC  (42+ messages)
` [PATCH v3 01/20] target/riscv: sync env->misa_ext* with cpu->cfg in realize()
` [PATCH v3 02/20] target/riscv: remove MISA properties from isa_edata_arr[]
` [PATCH v3 03/20] target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data
` [PATCH v3 04/20] target/riscv: introduce riscv_cpu_add_misa_properties()
` [PATCH v3 05/20] target/riscv: remove cpu->cfg.ext_a
` [PATCH v3 06/20] target/riscv: remove cpu->cfg.ext_c
` [PATCH v3 07/20] target/riscv: remove cpu->cfg.ext_d
` [PATCH v3 08/20] target/riscv: remove cpu->cfg.ext_f
` [PATCH v3 09/20] target/riscv: remove cpu->cfg.ext_i
` [PATCH v3 10/20] target/riscv: remove cpu->cfg.ext_e
` [PATCH v3 11/20] target/riscv: remove cpu->cfg.ext_m
` [PATCH v3 12/20] target/riscv: remove cpu->cfg.ext_s
` [PATCH v3 13/20] target/riscv: remove cpu->cfg.ext_u
` [PATCH v3 14/20] target/riscv: remove cpu->cfg.ext_h
` [PATCH v3 15/20] target/riscv: remove cpu->cfg.ext_j
` [PATCH v3 16/20] target/riscv: remove cpu->cfg.ext_v
` [PATCH v3 17/20] target/riscv: remove riscv_cpu_sync_misa_cfg()
` [PATCH v3 18/20] target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init()
` [PATCH v3 19/20] target/riscv: add RVG and remove cpu->cfg.ext_g
` [PATCH v3 20/20] target/riscv/cpu.c: redesign register_cpu_props()

[PATCH v3 0/4] target/riscv: Simplification for RVH related check and code style fix
 2023-04-05 23:04 UTC  (7+ messages)
` [PATCH v3 1/4] target/riscv: Remove riscv_cpu_virt_enabled()
` [PATCH v3 2/4] target/riscv: Fix format for indentation
` [PATCH v3 3/4] target/riscv: Fix format for comments
` [PATCH v3 4/4] target/riscv: Fix lines with over 80 characters

[PATCH] disas/riscv: Add support for XThead* instructions
 2023-04-05  6:45 UTC  (3+ messages)