From: Rajnesh Kanwal <rkanwal@rivosinc.com>
To: "Loïc Lefort" <loic@rivosinc.com>
Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, palmer@dabbelt.com,
alistair.francis@wdc.com, bin.meng@windriver.com,
liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, atishp@rivosinc.com,
apatel@ventanamicro.com
Subject: Re: [PATCH 2/6] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST.
Date: Thu, 18 May 2023 16:47:33 +0100 [thread overview]
Message-ID: <CAECbVCuMt7MHnRgPS_bo5dqhhEyeeGR11KtwZxQ0YR=Yj3RAag@mail.gmail.com> (raw)
In-Reply-To: <CAGKm2NK3+46Te9bFwmyAXkRy3RVXXe61Zz1BYdPaZqxMoJ7HHA@mail.gmail.com>
On Thu, May 18, 2023 at 4:21 PM Loïc Lefort <loic@rivosinc.com> wrote:
>
> Is there a reason to keep RISCV_EXCP_SEMIHOST handling separate from other exceptions?
> Otherwise it could be moved in the switch block just a few lines below.
I agree. I will move it to the switch in the next series.
Thanks
>
> On Thu, May 18, 2023 at 1:39 PM Rajnesh Kanwal <rkanwal@rivosinc.com> wrote:
>>
>> RISCV_EXCP_SEMIHOST is set to 0x10, which can also be a local
>> interrupt as well. This change adds a check for async flag
>> before invoking semihosting logic.
>>
>> Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
>> ---
>> target/riscv/cpu_helper.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
>> index 57d04385f1..c78a2a9514 100644
>> --- a/target/riscv/cpu_helper.c
>> +++ b/target/riscv/cpu_helper.c
>> @@ -1602,7 +1602,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
>> target_ulong htval = 0;
>> target_ulong mtval2 = 0;
>>
>> - if (cause == RISCV_EXCP_SEMIHOST) {
>> + if (!async && cause == RISCV_EXCP_SEMIHOST) {
>> do_common_semihosting(cs);
>> env->pc += 4;
>> return;
>> --
>> 2.25.1
>>
>>
next prev parent reply other threads:[~2023-05-18 15:48 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-18 11:38 [PATCH 0/6] Add RISC-V Virtual IRQs and IRQ filtering support Rajnesh Kanwal
2023-05-18 11:38 ` [PATCH 1/6] target/riscv: Without H-mode mask all HS mode inturrupts in mie Rajnesh Kanwal
2023-05-18 11:38 ` [PATCH 2/6] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST Rajnesh Kanwal
2023-05-18 15:20 ` Loïc Lefort
2023-05-18 15:47 ` Rajnesh Kanwal [this message]
2023-05-18 11:38 ` [PATCH 3/6] target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled Rajnesh Kanwal
2023-05-22 16:43 ` Daniel Henrique Barboza
2023-05-18 11:38 ` [PATCH 4/6] target/riscv: Split interrupt logic from riscv_cpu_update_mip Rajnesh Kanwal
2023-05-18 11:38 ` [PATCH 5/6] target/riscv: Add M-mode virtual interrupt and IRQ filtering support Rajnesh Kanwal
2023-05-18 11:38 ` [PATCH 6/6] target/riscv: Add HS-mode " Rajnesh Kanwal
2023-05-22 17:18 ` Daniel Henrique Barboza
2023-05-26 16:30 ` Rajnesh Kanwal
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