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To: Rajnesh Kanwal Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, atishp@rivosinc.com, apatel@ventanamicro.com Content-Type: multipart/alternative; boundary="00000000000007a7cd05fbf95a74" Received-SPF: pass client-ip=2607:f8b0:4864:20::1132; envelope-from=loic@rivosinc.com; helo=mail-yw1-x1132.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org --00000000000007a7cd05fbf95a74 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Is there a reason to keep RISCV_EXCP_SEMIHOST handling separate from other exceptions? Otherwise it could be moved in the switch block just a few lines below. On Thu, May 18, 2023 at 1:39=E2=80=AFPM Rajnesh Kanwal wrote: > RISCV_EXCP_SEMIHOST is set to 0x10, which can also be a local > interrupt as well. This change adds a check for async flag > before invoking semihosting logic. > > Signed-off-by: Rajnesh Kanwal > --- > target/riscv/cpu_helper.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 57d04385f1..c78a2a9514 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -1602,7 +1602,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) > target_ulong htval =3D 0; > target_ulong mtval2 =3D 0; > > - if (cause =3D=3D RISCV_EXCP_SEMIHOST) { > + if (!async && cause =3D=3D RISCV_EXCP_SEMIHOST) { > do_common_semihosting(cs); > env->pc +=3D 4; > return; > -- > 2.25.1 > > > --00000000000007a7cd05fbf95a74 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Is there a reason=C2=A0to keep RISCV_EXCP_SEMIHOST handlin= g=C2=A0separate from other=C2=A0exceptions?
Otherwise it could be moved= in the switch=C2=A0block just a few lines below.

On Thu, May 18, 2023= at 1:39=E2=80=AFPM Rajnesh Kanwal <rkanwal@rivosinc.com> wrote:
RISCV_EXCP_SEMIHOST is set to 0x10, which can also = be a local
interrupt as well. This change adds a check for async flag
before invoking semihosting logic.

Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
---
=C2=A0target/riscv/cpu_helper.c | 2 +-
=C2=A01 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 57d04385f1..c78a2a9514 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1602,7 +1602,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
=C2=A0 =C2=A0 =C2=A0target_ulong htval =3D 0;
=C2=A0 =C2=A0 =C2=A0target_ulong mtval2 =3D 0;

-=C2=A0 =C2=A0 if=C2=A0 (cause =3D=3D RISCV_EXCP_SEMIHOST) {
+=C2=A0 =C2=A0 if=C2=A0 (!async && cause =3D=3D RISCV_EXCP_SEMIHOST= ) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0do_common_semihosting(cs);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0env->pc +=3D 4;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return;
--
2.25.1


--00000000000007a7cd05fbf95a74--