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To: Tommy Wu Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, palmer@dabbelt.com, bin.meng@windriver.com, jim.shu@sifive.com, frank.chang@sifive.com, thuth@redhat.com, liweiwei@iscas.ac.cn Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::92f; envelope-from=alistair23@gmail.com; helo=mail-ua1-x92f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On Tue, May 23, 2023 at 6:50=E2=80=AFPM Tommy Wu wrot= e: > > Create the AON device when we realize the sifive_e machine. > This patch only implemented the functionality of the watchdog timer, > not all the functionality of the AON device. > > Signed-off-by: Tommy Wu > Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Alistair > --- > hw/riscv/Kconfig | 1 + > hw/riscv/sifive_e.c | 13 +++++++++++-- > include/hw/riscv/sifive_e.h | 8 +++++--- > 3 files changed, 17 insertions(+), 5 deletions(-) > > diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig > index 6528ebfa3a..b6a5eb4452 100644 > --- a/hw/riscv/Kconfig > +++ b/hw/riscv/Kconfig > @@ -60,6 +60,7 @@ config SIFIVE_E > select SIFIVE_PLIC > select SIFIVE_UART > select SIFIVE_E_PRCI > + select SIFIVE_E_AON > select UNIMP > > config SIFIVE_U > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c > index 04939b60c3..731ed0e11d 100644 > --- a/hw/riscv/sifive_e.c > +++ b/hw/riscv/sifive_e.c > @@ -45,6 +45,7 @@ > #include "hw/intc/riscv_aclint.h" > #include "hw/intc/sifive_plic.h" > #include "hw/misc/sifive_e_prci.h" > +#include "hw/misc/sifive_e_aon.h" > #include "chardev/char.h" > #include "sysemu/sysemu.h" > > @@ -223,8 +224,13 @@ static void sifive_e_soc_realize(DeviceState *dev, E= rror **errp) > RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus, > RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, > RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false); > - create_unimplemented_device("riscv.sifive.e.aon", > - memmap[SIFIVE_E_DEV_AON].base, memmap[SIFIVE_E_DEV_AON].size); > + > + s->aon =3D qdev_new(TYPE_SIFIVE_E_AON); > + if (!sysbus_realize(SYS_BUS_DEVICE(s->aon), errp)) { > + return; > + } > + sysbus_mmio_map(SYS_BUS_DEVICE(s->aon), 0, memmap[SIFIVE_E_DEV_AON].= base); > + > sifive_e_prci_create(memmap[SIFIVE_E_DEV_PRCI].base); > > /* GPIO */ > @@ -245,6 +251,9 @@ static void sifive_e_soc_realize(DeviceState *dev, Er= ror **errp) > qdev_get_gpio_in(DEVICE(s->plic), > SIFIVE_E_GPIO0_IRQ0 + i)); > } > + sysbus_connect_irq(SYS_BUS_DEVICE(s->aon), 0, > + qdev_get_gpio_in(DEVICE(s->plic), > + SIFIVE_E_AON_WDT_IRQ)); > > sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART0].base, > serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_I= RQ)); > diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h > index b824a79e2d..a094b47e0b 100644 > --- a/include/hw/riscv/sifive_e.h > +++ b/include/hw/riscv/sifive_e.h > @@ -35,6 +35,7 @@ typedef struct SiFiveESoCState { > /*< public >*/ > RISCVHartArrayState cpus; > DeviceState *plic; > + DeviceState *aon; > SIFIVEGPIOState gpio; > MemoryRegion xip_mem; > MemoryRegion mask_rom; > @@ -76,9 +77,10 @@ enum { > }; > > enum { > - SIFIVE_E_UART0_IRQ =3D 3, > - SIFIVE_E_UART1_IRQ =3D 4, > - SIFIVE_E_GPIO0_IRQ0 =3D 8 > + SIFIVE_E_AON_WDT_IRQ =3D 1, > + SIFIVE_E_UART0_IRQ =3D 3, > + SIFIVE_E_UART1_IRQ =3D 4, > + SIFIVE_E_GPIO0_IRQ0 =3D 8 > }; > > #define SIFIVE_E_PLIC_HART_CONFIG "M" > -- > 2.27.0 > >