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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::a2e; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa2e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On Tue, May 30, 2023 at 11:21=E2=80=AFPM Christoph Muellner wrote: > > From: Christoph M=C3=BCllner > > A previous patch provides a pointer to the RISCVCPUConfig data. > Let's use this to add the necessary code for vendor extensions. > This patch does not change the current behaviour, but clearly > defines how vendor extension support can be added to the disassembler. > > Signed-off-by: Christoph M=C3=BCllner Reviewed-by: Alistair Francis Alistair > --- > disas/riscv.c | 34 ++++++++++++++++++++++++++++++---- > 1 file changed, 30 insertions(+), 4 deletions(-) > > diff --git a/disas/riscv.c b/disas/riscv.c > index 086edee6a2..db98e3ea6a 100644 > --- a/disas/riscv.c > +++ b/disas/riscv.c > @@ -20,6 +20,7 @@ > #include "qemu/osdep.h" > #include "disas/dis-asm.h" > #include "disas/riscv.h" > +#include "target/riscv/cpu-config.h" > > typedef enum { > /* 0 is reserved for rv_op_illegal. */ > @@ -4599,13 +4600,38 @@ static void decode_inst_decompress(rv_decode *dec= , rv_isa isa) > /* disassemble instruction */ > > static void > -disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst i= nst) > +disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst i= nst, > + struct disassemble_info *info) > { > + RISCVCPUConfig *cfg =3D info->private_data; > rv_decode dec =3D { 0 }; > dec.pc =3D pc; > dec.inst =3D inst; > - dec.opcode_data =3D rvi_opcode_data; > - decode_inst_opcode(&dec, isa); > + > + static const struct { > + bool (*guard_func)(const RISCVCPUConfig *); > + const rv_opcode_data *opcode_data; > + void (*decode_func)(rv_decode *, rv_isa); > + } decoders[] =3D { > + { always_true_p, rvi_opcode_data, decode_inst_opcode }, > + }; > + > + for (size_t i =3D 0; i < ARRAY_SIZE(decoders); i++) { > + bool (*guard_func)(const RISCVCPUConfig *) =3D decoders[i].guard= _func; > + const rv_opcode_data *opcode_data =3D decoders[i].opcode_data; > + void (*decode_func)(rv_decode *, rv_isa) =3D decoders[i].decode_= func; > + > + if (guard_func(cfg)) { > + dec.opcode_data =3D opcode_data; > + decode_func(&dec, isa); > + if (dec.op !=3D rv_op_illegal) > + break; > + } > + } > + > + if (dec.op =3D=3D rv_op_illegal) > + dec.opcode_data =3D rvi_opcode_data; > + > decode_inst_operands(&dec, isa); > decode_inst_decompress(&dec, isa); > decode_inst_lift_pseudo(&dec); > @@ -4659,7 +4685,7 @@ print_insn_riscv(bfd_vma memaddr, struct disassembl= e_info *info, rv_isa isa) > break; > } > > - disasm_inst(buf, sizeof(buf), isa, memaddr, inst); > + disasm_inst(buf, sizeof(buf), isa, memaddr, inst, info); > (*info->fprintf_func)(info->stream, "%s", buf); > > return len; > -- > 2.40.1 > >