From: Jason Gunthorpe <jgg@nvidia.com> To: iommu@lists.linux.dev, Joerg Roedel <joro@8bytes.org>, linux-arm-kernel@lists.infradead.org, Robin Murphy <robin.murphy@arm.com>, Will Deacon <will@kernel.org> Cc: Jean-Philippe Brucker <jean-philippe@linaro.org>, Michael Shavit <mshavit@google.com>, Nicolin Chen <nicolinc@nvidia.com> Subject: [PATCH 00/27] Update SMMUv3 to the modern iommu API (part 2/2) Date: Wed, 11 Oct 2023 20:25:36 -0300 [thread overview] Message-ID: <0-v1-afbb86647bbd+5-smmuv3_newapi_p2_jgg@nvidia.com> (raw) Continuing the work of part 1 this focuses on the CD, PASID and SVA components: - attach_dev failure does not change the HW configuration. - Full PASID API support including: - S1/SVA domains attached to PASIDs - IDENTITY/BLOCKED/S1 attached to RID - Change of the RID domain while PASIDs are attached - Streamlined SVA support using the core infrastructure - Hitless, whenever possible, change between two domains Making the CD programming work like the new STE programming allows untangling some of the confusing SVA flows. From there the focus is on building out the core infrastructure for dealing with PASID and CD entries, then keeping track of unique SSID's for ATS invalidation. The ATS ordering is generalized so that the PASID flow can use it and put into a form where it is fully hitless, whenever possible. Finally we simply kill the entire outdated SVA mmu_notifier implementation in one shot and switch it over to the newly created generic PASID & CD code. This avoids the messy and confusing approach of trying to incrementally untangle this in place. The new code is small and simple enough this is much better than trying to figure out fixes. Once SVA is resting on the right CD code it is straightforward to make the PASID interface functionally complete. This depends on part 1 The SVA change requires Tina's series: https://lore.kernel.org/linux-iommu/20230925023813.575016-1-tina.zhang@intel.com/ (Although if you have only a single SVA device it is not necessary to test) It achives the same goals as the several series from Michael and the S1DSS series from Nicolin that were trying to improve portions of the API. There are still topics for a part 3 (as yet unwritten) which would want to make iommu_domains work across instances, split the s1/2 domain ops, and further polish some of the code. This is on github: https://github.com/jgunthorpe/linux/commits/smmuv3_newapi Jason Gunthorpe (27): iommu/arm-smmu-v3: Check that the RID domain is S1 in SVA iommu/arm-smmu-v3: Do not allow a SVA domain to be set on the wrong PASID iommu/arm-smmu-v3: Do not ATC invalidate the entire domain iommu/arm-smmu-v3: Add a type for the CD entry iommu/arm-smmu-v3: Make CD programming use arm_smmu_write_entry_step() iommu/arm-smmu-v3: Consolidate clearing a CD table entry iommu/arm-smmu-v3: Move the CD generation for S1 domains into a function iommu/arm-smmu-v3: Move allocation of the cdtable into arm_smmu_get_cd_ptr() iommu/arm-smmu-v3: Allocate the CD table entry in advance iommu/arm-smmu-v3: Move the CD generation for SVA into a function iommu/arm-smmu-v3: Lift CD programming out of the SVA notifier code iommu/arm-smmu-v3: Build the whole CD in arm_smmu_make_s1_cd() iommu/arm-smmu-v3: Make smmu_domain->devices into an allocated list iommu/arm-smmu-v3: Make changing domains be hitless for ATS iommu/arm-smmu-v3: Add ssid to struct arm_smmu_master_domain iommu/arm-smmu-v3: Keep track of valid CD entries in the cd_table iommu/arm-smmu-v3: Thread SSID through the arm_smmu_attach_*() interface iommu/arm-smmu-v3: Make SVA allocate a normal arm_smmu_domain iommu/arm-smmu-v3: Keep track of arm_smmu_master_domain for SVA iommu: Add ops->domain_alloc_sva() iommu/arm-smmu-v3: Put the SVA mmu notifier in the smmu_domain iommu/arm-smmu-v3: Consolidate freeing the ASID/VMID iommu/arm-smmu-v3: Move the arm_smmu_asid_xa to per-smmu like vmid iommu/arm-smmu-v3: Bring back SVA BTM support iommu/arm-smmu-v3: Allow IDENTITY/BLOCKED to be set while PASID is used iommu/arm-smmu-v3: Allow a PASID to be set when RID is IDENTITY/BLOCKED iommu/arm-smmu-v3: Allow setting a S1 domain to a PASID .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 620 ++++++------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 846 ++++++++++++------ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 94 +- drivers/iommu/iommu-sva.c | 4 +- drivers/iommu/iommu.c | 12 +- include/linux/iommu.h | 3 + 6 files changed, 888 insertions(+), 691 deletions(-) base-commit: 0f6f4b2cc77710aef8d0734a27206f1e1e9a360d -- 2.42.0
WARNING: multiple messages have this Message-ID (diff)
From: Jason Gunthorpe <jgg@nvidia.com> To: iommu@lists.linux.dev, Joerg Roedel <joro@8bytes.org>, linux-arm-kernel@lists.infradead.org, Robin Murphy <robin.murphy@arm.com>, Will Deacon <will@kernel.org> Cc: Jean-Philippe Brucker <jean-philippe@linaro.org>, Michael Shavit <mshavit@google.com>, Nicolin Chen <nicolinc@nvidia.com> Subject: [PATCH 00/27] Update SMMUv3 to the modern iommu API (part 2/2) Date: Wed, 11 Oct 2023 20:25:36 -0300 [thread overview] Message-ID: <0-v1-afbb86647bbd+5-smmuv3_newapi_p2_jgg@nvidia.com> (raw) Continuing the work of part 1 this focuses on the CD, PASID and SVA components: - attach_dev failure does not change the HW configuration. - Full PASID API support including: - S1/SVA domains attached to PASIDs - IDENTITY/BLOCKED/S1 attached to RID - Change of the RID domain while PASIDs are attached - Streamlined SVA support using the core infrastructure - Hitless, whenever possible, change between two domains Making the CD programming work like the new STE programming allows untangling some of the confusing SVA flows. From there the focus is on building out the core infrastructure for dealing with PASID and CD entries, then keeping track of unique SSID's for ATS invalidation. The ATS ordering is generalized so that the PASID flow can use it and put into a form where it is fully hitless, whenever possible. Finally we simply kill the entire outdated SVA mmu_notifier implementation in one shot and switch it over to the newly created generic PASID & CD code. This avoids the messy and confusing approach of trying to incrementally untangle this in place. The new code is small and simple enough this is much better than trying to figure out fixes. Once SVA is resting on the right CD code it is straightforward to make the PASID interface functionally complete. This depends on part 1 The SVA change requires Tina's series: https://lore.kernel.org/linux-iommu/20230925023813.575016-1-tina.zhang@intel.com/ (Although if you have only a single SVA device it is not necessary to test) It achives the same goals as the several series from Michael and the S1DSS series from Nicolin that were trying to improve portions of the API. There are still topics for a part 3 (as yet unwritten) which would want to make iommu_domains work across instances, split the s1/2 domain ops, and further polish some of the code. This is on github: https://github.com/jgunthorpe/linux/commits/smmuv3_newapi Jason Gunthorpe (27): iommu/arm-smmu-v3: Check that the RID domain is S1 in SVA iommu/arm-smmu-v3: Do not allow a SVA domain to be set on the wrong PASID iommu/arm-smmu-v3: Do not ATC invalidate the entire domain iommu/arm-smmu-v3: Add a type for the CD entry iommu/arm-smmu-v3: Make CD programming use arm_smmu_write_entry_step() iommu/arm-smmu-v3: Consolidate clearing a CD table entry iommu/arm-smmu-v3: Move the CD generation for S1 domains into a function iommu/arm-smmu-v3: Move allocation of the cdtable into arm_smmu_get_cd_ptr() iommu/arm-smmu-v3: Allocate the CD table entry in advance iommu/arm-smmu-v3: Move the CD generation for SVA into a function iommu/arm-smmu-v3: Lift CD programming out of the SVA notifier code iommu/arm-smmu-v3: Build the whole CD in arm_smmu_make_s1_cd() iommu/arm-smmu-v3: Make smmu_domain->devices into an allocated list iommu/arm-smmu-v3: Make changing domains be hitless for ATS iommu/arm-smmu-v3: Add ssid to struct arm_smmu_master_domain iommu/arm-smmu-v3: Keep track of valid CD entries in the cd_table iommu/arm-smmu-v3: Thread SSID through the arm_smmu_attach_*() interface iommu/arm-smmu-v3: Make SVA allocate a normal arm_smmu_domain iommu/arm-smmu-v3: Keep track of arm_smmu_master_domain for SVA iommu: Add ops->domain_alloc_sva() iommu/arm-smmu-v3: Put the SVA mmu notifier in the smmu_domain iommu/arm-smmu-v3: Consolidate freeing the ASID/VMID iommu/arm-smmu-v3: Move the arm_smmu_asid_xa to per-smmu like vmid iommu/arm-smmu-v3: Bring back SVA BTM support iommu/arm-smmu-v3: Allow IDENTITY/BLOCKED to be set while PASID is used iommu/arm-smmu-v3: Allow a PASID to be set when RID is IDENTITY/BLOCKED iommu/arm-smmu-v3: Allow setting a S1 domain to a PASID .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 620 ++++++------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 846 ++++++++++++------ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 94 +- drivers/iommu/iommu-sva.c | 4 +- drivers/iommu/iommu.c | 12 +- include/linux/iommu.h | 3 + 6 files changed, 888 insertions(+), 691 deletions(-) base-commit: 0f6f4b2cc77710aef8d0734a27206f1e1e9a360d -- 2.42.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next reply other threads:[~2023-10-11 23:26 UTC|newest] Thread overview: 88+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-10-11 23:25 Jason Gunthorpe [this message] 2023-10-11 23:25 ` [PATCH 00/27] Update SMMUv3 to the modern iommu API (part 2/2) Jason Gunthorpe 2023-10-11 23:25 ` [PATCH 01/27] iommu/arm-smmu-v3: Check that the RID domain is S1 in SVA Jason Gunthorpe 2023-10-11 23:25 ` Jason Gunthorpe 2023-10-11 23:25 ` [PATCH 02/27] iommu/arm-smmu-v3: Do not allow a SVA domain to be set on the wrong PASID Jason Gunthorpe 2023-10-11 23:25 ` Jason Gunthorpe 2023-10-11 23:25 ` [PATCH 03/27] iommu/arm-smmu-v3: Do not ATC invalidate the entire domain Jason Gunthorpe 2023-10-11 23:25 ` Jason Gunthorpe 2023-10-11 23:25 ` [PATCH 04/27] iommu/arm-smmu-v3: Add a type for the CD entry Jason Gunthorpe 2023-10-11 23:25 ` Jason Gunthorpe 2023-10-11 23:25 ` [PATCH 05/27] iommu/arm-smmu-v3: Make CD programming use arm_smmu_write_entry_step() Jason Gunthorpe 2023-10-11 23:25 ` Jason Gunthorpe 2023-10-11 23:25 ` [PATCH 06/27] iommu/arm-smmu-v3: Consolidate clearing a CD table entry Jason Gunthorpe 2023-10-11 23:25 ` Jason Gunthorpe 2023-10-11 23:25 ` [PATCH 07/27] iommu/arm-smmu-v3: Move the CD generation for S1 domains into a function Jason Gunthorpe 2023-10-11 23:25 ` Jason Gunthorpe 2023-10-11 23:25 ` [PATCH 08/27] iommu/arm-smmu-v3: Move allocation of the cdtable into arm_smmu_get_cd_ptr() Jason Gunthorpe 2023-10-11 23:25 ` Jason Gunthorpe 2023-10-11 23:25 ` [PATCH 09/27] iommu/arm-smmu-v3: Allocate the CD table entry in advance Jason Gunthorpe 2023-10-11 23:25 ` Jason Gunthorpe 2023-10-11 23:25 ` [PATCH 10/27] iommu/arm-smmu-v3: Move the CD generation for SVA into a function Jason Gunthorpe 2023-10-11 23:25 ` Jason Gunthorpe 2023-10-24 4:12 ` Michael Shavit 2023-10-24 4:12 ` Michael Shavit 2023-10-24 11:52 ` Jason Gunthorpe 2023-10-24 11:52 ` Jason Gunthorpe 2023-10-11 23:25 ` [PATCH 11/27] iommu/arm-smmu-v3: Lift CD programming out of the SVA notifier code Jason Gunthorpe 2023-10-11 23:25 ` Jason Gunthorpe 2023-10-24 6:34 ` Michael Shavit 2023-10-24 6:34 ` Michael Shavit 2023-10-24 23:46 ` Jason Gunthorpe 2023-10-24 23:46 ` Jason Gunthorpe 2023-10-26 7:31 ` Michael Shavit 2023-10-26 7:31 ` Michael Shavit 2023-10-26 14:11 ` Jason Gunthorpe 2023-10-26 14:11 ` Jason Gunthorpe 2023-10-11 23:25 ` [PATCH 12/27] iommu/arm-smmu-v3: Build the whole CD in arm_smmu_make_s1_cd() Jason Gunthorpe 2023-10-11 23:25 ` Jason Gunthorpe 2023-10-11 23:25 ` [PATCH 13/27] iommu/arm-smmu-v3: Make smmu_domain->devices into an allocated list Jason Gunthorpe 2023-10-11 23:25 ` Jason Gunthorpe 2023-10-11 23:25 ` [PATCH 14/27] iommu/arm-smmu-v3: Make changing domains be hitless for ATS Jason Gunthorpe 2023-10-11 23:25 ` Jason Gunthorpe 2023-10-24 8:09 ` Michael Shavit 2023-10-24 8:09 ` Michael Shavit 2023-10-24 23:56 ` Jason Gunthorpe 2023-10-24 23:56 ` Jason Gunthorpe 2023-10-26 7:00 ` Michael Shavit 2023-10-26 7:00 ` Michael Shavit 2023-10-26 14:38 ` Jason Gunthorpe 2023-10-26 14:38 ` Jason Gunthorpe 2023-10-11 23:25 ` [PATCH 15/27] iommu/arm-smmu-v3: Add ssid to struct arm_smmu_master_domain Jason Gunthorpe 2023-10-11 23:25 ` Jason Gunthorpe 2023-10-11 23:25 ` [PATCH 16/27] iommu/arm-smmu-v3: Keep track of valid CD entries in the cd_table Jason Gunthorpe 2023-10-11 23:25 ` Jason Gunthorpe 2023-10-11 23:25 ` [PATCH 17/27] iommu/arm-smmu-v3: Thread SSID through the arm_smmu_attach_*() interface Jason Gunthorpe 2023-10-11 23:25 ` Jason Gunthorpe 2023-10-25 14:01 ` Jason Gunthorpe 2023-10-25 14:01 ` Jason Gunthorpe 2023-10-11 23:25 ` [PATCH 18/27] iommu/arm-smmu-v3: Make SVA allocate a normal arm_smmu_domain Jason Gunthorpe 2023-10-11 23:25 ` Jason Gunthorpe 2023-10-24 8:58 ` Michael Shavit 2023-10-24 8:58 ` Michael Shavit 2023-10-24 13:05 ` Jason Gunthorpe 2023-10-24 13:05 ` Jason Gunthorpe 2023-10-11 23:25 ` [PATCH 19/27] iommu/arm-smmu-v3: Keep track of arm_smmu_master_domain for SVA Jason Gunthorpe 2023-10-11 23:25 ` Jason Gunthorpe 2023-10-11 23:25 ` [PATCH 20/27] iommu: Add ops->domain_alloc_sva() Jason Gunthorpe 2023-10-11 23:25 ` Jason Gunthorpe 2023-10-11 23:25 ` [PATCH 21/27] iommu/arm-smmu-v3: Put the SVA mmu notifier in the smmu_domain Jason Gunthorpe 2023-10-11 23:25 ` Jason Gunthorpe 2023-10-25 13:56 ` Jason Gunthorpe 2023-10-25 13:56 ` Jason Gunthorpe 2023-10-25 16:23 ` Jason Gunthorpe 2023-10-25 16:23 ` Jason Gunthorpe 2023-10-11 23:25 ` [PATCH 22/27] iommu/arm-smmu-v3: Consolidate freeing the ASID/VMID Jason Gunthorpe 2023-10-11 23:25 ` Jason Gunthorpe 2023-10-11 23:25 ` [PATCH 23/27] iommu/arm-smmu-v3: Move the arm_smmu_asid_xa to per-smmu like vmid Jason Gunthorpe 2023-10-11 23:25 ` Jason Gunthorpe 2023-10-11 23:26 ` [PATCH 24/27] iommu/arm-smmu-v3: Bring back SVA BTM support Jason Gunthorpe 2023-10-11 23:26 ` Jason Gunthorpe 2023-10-11 23:26 ` [PATCH 25/27] iommu/arm-smmu-v3: Allow IDENTITY/BLOCKED to be set while PASID is used Jason Gunthorpe 2023-10-11 23:26 ` Jason Gunthorpe 2023-10-25 15:10 ` Jason Gunthorpe 2023-10-25 15:10 ` Jason Gunthorpe 2023-10-11 23:26 ` [PATCH 26/27] iommu/arm-smmu-v3: Allow a PASID to be set when RID is IDENTITY/BLOCKED Jason Gunthorpe 2023-10-11 23:26 ` Jason Gunthorpe 2023-10-11 23:26 ` [PATCH 27/27] iommu/arm-smmu-v3: Allow setting a S1 domain to a PASID Jason Gunthorpe 2023-10-11 23:26 ` Jason Gunthorpe
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