From: Chen Wang <unicornxw@gmail.com> To: adrian.hunter@intel.com, aou@eecs.berkeley.edu, conor+dt@kernel.org, guoren@kernel.org, inochiama@outlook.com, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh@kernel.org, ulf.hansson@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-riscv@lists.infradead.org, chao.wei@sophgo.com, haijiao.liu@sophgo.com, xiaoguang.xing@sophgo.com, tingzhu.wang@sophgo.com Cc: Chen Wang <unicorn_wang@outlook.com> Subject: [PATCH 1/3] dt-bindings: mmc: sdhci-of-dwcmhsc: Add Sophgo SG2042 support Date: Tue, 16 Apr 2024 17:50:37 +0800 [thread overview] Message-ID: <032c06642b01f06c86ba8bcd2108d18c005b57eb.1713258948.git.unicorn_wang@outlook.com> (raw) In-Reply-To: <cover.1713258948.git.unicorn_wang@outlook.com> From: Chen Wang <unicorn_wang@outlook.com> SG2042 use Synopsys dwcnshc IP for SD/eMMC controllers. SG2042 defines 3 clocks for SD/eMMC controllers. - AXI_EMMC/AXI_SD for aclk/hclk(Bus interface clocks in DWC_mshc) and blck(Core Base Clock in DWC_mshc), these 3 clocks share one source, so reuse existing "core". - 100K_EMMC/100K_SD for cqetmclk(Timer clocks in DWC_mshc), so reuse existing "timer" which was added for rockchip specified. - EMMC_100M/SD_100M for cclk(Card clocks in DWC_mshc), add new "card". Adding some examples. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> --- .../bindings/mmc/snps,dwcmshc-sdhci.yaml | 67 ++++++++++++++----- 1 file changed, 51 insertions(+), 16 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml index 4d3031d9965f..a04ccae216cf 100644 --- a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml @@ -21,6 +21,7 @@ properties: - snps,dwcmshc-sdhci - sophgo,cv1800b-dwcmshc - sophgo,sg2002-dwcmshc + - sophgo,sg2042-dwcmshc - thead,th1520-dwcmshc reg: @@ -30,23 +31,36 @@ properties: maxItems: 1 clocks: - minItems: 1 - items: - - description: core clock - - description: bus clock for optional - - description: axi clock for rockchip specified - - description: block clock for rockchip specified - - description: timer clock for rockchip specified - + anyOf: + - minItems: 1 + items: + - description: core clock + - description: bus clock for optional + - description: axi clock for rockchip specified + - description: block clock for rockchip specified + - description: timer clock for rockchip specified + + - minItems: 1 + items: + - description: core clock + - description: timer clock + - description: card clock clock-names: - minItems: 1 - items: - - const: core - - const: bus - - const: axi - - const: block - - const: timer + anyOf: + - minItems: 1 + items: + - const: core + - const: bus + - const: axi + - const: block + - const: timer + + - minItems: 1 + items: + - const: core + - const: timer + - const: card resets: maxItems: 5 @@ -96,5 +110,26 @@ examples: #address-cells = <1>; #size-cells = <0>; }; - + - | + mmc@bb0000 { + compatible = "snps,dwcmshc-sdhci"; + reg = <0xbb000 0x1000>; + interrupts = <0 25 0x4>; + clocks = <&cru 17>; + clock-names = "core"; + bus-width = <8>; + #address-cells = <1>; + #size-cells = <0>; + }; + - | + mmc@cc0000 { + compatible = "snps,dwcmshc-sdhci"; + reg = <0xcc000 0x1000>; + interrupts = <0 25 0x4>; + clocks = <&cru 17>, <&cru 18>, <&cru 19>; + clock-names = "core", "timer", "card"; + bus-width = <8>; + #address-cells = <1>; + #size-cells = <0>; + }; ... -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Chen Wang <unicornxw@gmail.com> To: adrian.hunter@intel.com, aou@eecs.berkeley.edu, conor+dt@kernel.org, guoren@kernel.org, inochiama@outlook.com, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh@kernel.org, ulf.hansson@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-riscv@lists.infradead.org, chao.wei@sophgo.com, haijiao.liu@sophgo.com, xiaoguang.xing@sophgo.com, tingzhu.wang@sophgo.com Cc: Chen Wang <unicorn_wang@outlook.com> Subject: [PATCH 1/3] dt-bindings: mmc: sdhci-of-dwcmhsc: Add Sophgo SG2042 support Date: Tue, 16 Apr 2024 17:50:37 +0800 [thread overview] Message-ID: <032c06642b01f06c86ba8bcd2108d18c005b57eb.1713258948.git.unicorn_wang@outlook.com> (raw) In-Reply-To: <cover.1713258948.git.unicorn_wang@outlook.com> From: Chen Wang <unicorn_wang@outlook.com> SG2042 use Synopsys dwcnshc IP for SD/eMMC controllers. SG2042 defines 3 clocks for SD/eMMC controllers. - AXI_EMMC/AXI_SD for aclk/hclk(Bus interface clocks in DWC_mshc) and blck(Core Base Clock in DWC_mshc), these 3 clocks share one source, so reuse existing "core". - 100K_EMMC/100K_SD for cqetmclk(Timer clocks in DWC_mshc), so reuse existing "timer" which was added for rockchip specified. - EMMC_100M/SD_100M for cclk(Card clocks in DWC_mshc), add new "card". Adding some examples. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> --- .../bindings/mmc/snps,dwcmshc-sdhci.yaml | 67 ++++++++++++++----- 1 file changed, 51 insertions(+), 16 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml index 4d3031d9965f..a04ccae216cf 100644 --- a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml @@ -21,6 +21,7 @@ properties: - snps,dwcmshc-sdhci - sophgo,cv1800b-dwcmshc - sophgo,sg2002-dwcmshc + - sophgo,sg2042-dwcmshc - thead,th1520-dwcmshc reg: @@ -30,23 +31,36 @@ properties: maxItems: 1 clocks: - minItems: 1 - items: - - description: core clock - - description: bus clock for optional - - description: axi clock for rockchip specified - - description: block clock for rockchip specified - - description: timer clock for rockchip specified - + anyOf: + - minItems: 1 + items: + - description: core clock + - description: bus clock for optional + - description: axi clock for rockchip specified + - description: block clock for rockchip specified + - description: timer clock for rockchip specified + + - minItems: 1 + items: + - description: core clock + - description: timer clock + - description: card clock clock-names: - minItems: 1 - items: - - const: core - - const: bus - - const: axi - - const: block - - const: timer + anyOf: + - minItems: 1 + items: + - const: core + - const: bus + - const: axi + - const: block + - const: timer + + - minItems: 1 + items: + - const: core + - const: timer + - const: card resets: maxItems: 5 @@ -96,5 +110,26 @@ examples: #address-cells = <1>; #size-cells = <0>; }; - + - | + mmc@bb0000 { + compatible = "snps,dwcmshc-sdhci"; + reg = <0xbb000 0x1000>; + interrupts = <0 25 0x4>; + clocks = <&cru 17>; + clock-names = "core"; + bus-width = <8>; + #address-cells = <1>; + #size-cells = <0>; + }; + - | + mmc@cc0000 { + compatible = "snps,dwcmshc-sdhci"; + reg = <0xcc000 0x1000>; + interrupts = <0 25 0x4>; + clocks = <&cru 17>, <&cru 18>, <&cru 19>; + clock-names = "core", "timer", "card"; + bus-width = <8>; + #address-cells = <1>; + #size-cells = <0>; + }; ... -- 2.25.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2024-04-16 9:50 UTC|newest] Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-04-16 9:50 [PATCH 0/3] mmc: sdhci-of-dwcmshc: support Sophgo SG2042 Chen Wang 2024-04-16 9:50 ` Chen Wang 2024-04-16 9:50 ` Chen Wang [this message] 2024-04-16 9:50 ` [PATCH 1/3] dt-bindings: mmc: sdhci-of-dwcmhsc: Add Sophgo SG2042 support Chen Wang 2024-04-16 16:44 ` Conor Dooley 2024-04-16 16:44 ` Conor Dooley 2024-04-17 0:00 ` Chen Wang 2024-04-17 0:00 ` Chen Wang 2024-04-16 9:50 ` [PATCH 2/3] mmc: sdhci-of-dwcmshc: Add support for Sophgo SG2042 Chen Wang 2024-04-16 9:50 ` Chen Wang 2024-04-16 15:37 ` Jisheng Zhang 2024-04-16 15:37 ` Jisheng Zhang 2024-04-16 23:53 ` Chen Wang 2024-04-16 23:53 ` Chen Wang 2024-04-16 9:51 ` [PATCH 3/3] riscv: dts: add mmc controllers for Sophgo SG2042 SoC Chen Wang 2024-04-16 9:51 ` Chen Wang
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