From: Jan Beulich <jbeulich@suse.com>
To: "xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>
Cc: "Andrew Cooper" <andrew.cooper3@citrix.com>,
"Wei Liu" <wl@xen.org>, "Roger Pau Monné" <roger.pau@citrix.com>
Subject: [Xen-devel] [PATCH v3] x86: explicitly disallow guest access to PPIN
Date: Fri, 20 Dec 2019 15:25:08 +0100 [thread overview]
Message-ID: <05cc35aa-ebb0-1316-bbcc-790533f21b25@suse.com> (raw)
To fulfill the "protected" in its name, don't let the real hardware
values leak. While we could report a control register value expressing
this (which I would have preferred), unconditionally raise #GP for all
accesses (in the interest of getting this done).
Signed-off-by: Jan Beulich <jbeulich@suse.com>
---
v3: Unconditional #GP in guest_rdmsr(). Adjust case label placement in
guest_wrmsr().
v2: Use "cp" consistently. Re-base.
--- a/xen/arch/x86/msr.c
+++ b/xen/arch/x86/msr.c
@@ -136,6 +136,10 @@ int guest_rdmsr(struct vcpu *v, uint32_t
case MSR_TSX_CTRL:
case MSR_AMD64_LWP_CFG:
case MSR_AMD64_LWP_CBADDR:
+ case MSR_PPIN_CTL:
+ case MSR_PPIN:
+ case MSR_AMD_PPIN_CTL:
+ case MSR_AMD_PPIN:
/* Not offered to guests. */
goto gp_fault;
@@ -279,6 +283,10 @@ int guest_wrmsr(struct vcpu *v, uint32_t
case MSR_TSX_CTRL:
case MSR_AMD64_LWP_CFG:
case MSR_AMD64_LWP_CBADDR:
+ case MSR_PPIN_CTL:
+ case MSR_PPIN:
+ case MSR_AMD_PPIN_CTL:
+ case MSR_AMD_PPIN:
/* Not offered to guests. */
goto gp_fault;
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next reply other threads:[~2019-12-20 14:24 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-20 14:25 Jan Beulich [this message]
2019-12-20 14:37 ` [Xen-devel] [PATCH v3] x86: explicitly disallow guest access to PPIN Andrew Cooper
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