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From: Jesse Barnes <jbarnes@virtuousgeek.org>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 1/5] drm/i915: cleanup FBC buffers at unload time
Date: Wed, 21 Apr 2010 11:39:22 -0700	[thread overview]
Message-ID: <1271875166-13084-2-git-send-email-jbarnes@virtuousgeek.org> (raw)
In-Reply-To: <1271875166-13084-1-git-send-email-jbarnes@virtuousgeek.org>

This keeps the memory manager from complaining when we take it down.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_dma.c |   14 ++++++++++++++
 drivers/gpu/drm/i915/i915_drv.h |    3 +++
 2 files changed, 17 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 75248be..5853d57 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1356,6 +1356,8 @@ static void i915_setup_compression(struct drm_device *dev, int size)
 
 	dev_priv->cfb_size = size;
 
+	dev_priv->compressed_fb = compressed_fb;
+
 	if (IS_GM45(dev)) {
 		g4x_disable_fbc(dev);
 		I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
@@ -1363,12 +1365,22 @@ static void i915_setup_compression(struct drm_device *dev, int size)
 		i8xx_disable_fbc(dev);
 		I915_WRITE(FBC_CFB_BASE, cfb_base);
 		I915_WRITE(FBC_LL_BASE, ll_base);
+		dev_priv->compressed_llb = compressed_llb;
 	}
 
 	DRM_DEBUG("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base,
 		  ll_base, size >> 20);
 }
 
+static void i915_cleanup_compression(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	drm_mm_put_block(dev_priv->compressed_fb);
+	if (!IS_GM45(dev))
+		drm_mm_put_block(dev_priv->compressed_llb);
+}
+
 /* true = enable decode, false = disable decoder */
 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 {
@@ -1788,6 +1800,8 @@ int i915_driver_unload(struct drm_device *dev)
 		mutex_lock(&dev->struct_mutex);
 		i915_gem_cleanup_ringbuffer(dev);
 		mutex_unlock(&dev->struct_mutex);
+		if (I915_HAS_FBC(dev) && i915_powersave)
+			i915_cleanup_compression(dev);
 		drm_mm_takedown(&dev_priv->vram);
 		i915_gem_lastclose(dev);
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 790fef3..b3e6678 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -638,6 +638,9 @@ typedef struct drm_i915_private {
 	u8 max_delay;
 
 	enum no_fbc_reason no_fbc_reason;
+
+	struct drm_mm_node *compressed_fb;
+	struct drm_mm_node *compressed_llb;
 } drm_i915_private_t;
 
 /** driver private structure attached to each drm_gem_object */
-- 
1.7.0.1

  reply	other threads:[~2010-04-21 18:38 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-04-21 18:39 Use PIPE_CONTROL where possible Jesse Barnes
2010-04-21 18:39 ` Jesse Barnes [this message]
2010-04-21 18:39 ` [PATCH 2/5] drm/i915: use PIPE_CONTROL instruction on Ironlake and Sandy Bridge Jesse Barnes
2010-04-21 18:39 ` [PATCH 3/5] drm/i915: use PIPE_CONTROL to retire commands Jesse Barnes
2010-04-29 21:26   ` Eric Anholt
2010-05-03 19:41     ` Jesse Barnes
2010-04-21 18:39 ` [PATCH 4/5] drm/i915: use PIPE_CONTROL for GEM domain flushing Jesse Barnes
2010-04-21 18:39 ` [PATCH 5/5] drm/i915: enable PIPE_CONTROL on all 965 class chips Jesse Barnes
2010-04-21 19:49   ` [PATCH] drm/i915: avoid unnecessary PIPE_CONTROL flushing on non-Ironlake Jesse Barnes
2010-04-21 20:02   ` [PATCH] drm/i915: remove unnecessary PIPE_CONTROL cache flushing Jesse Barnes

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