From: Jesse Barnes <jbarnes@virtuousgeek.org>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 3/5] drm/i915: use PIPE_CONTROL to retire commands
Date: Wed, 21 Apr 2010 11:39:24 -0700 [thread overview]
Message-ID: <1271875166-13084-4-git-send-email-jbarnes@virtuousgeek.org> (raw)
In-Reply-To: <1271875166-13084-1-git-send-email-jbarnes@virtuousgeek.org>
This allows us to do less cache flushing on 965+ chipsets.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/i915_gem.c | 25 +++++++++++++++++--------
1 files changed, 17 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e7fc200..21bfaae 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1707,17 +1707,26 @@ static uint32_t
i915_retire_commands(struct drm_device *dev)
{
drm_i915_private_t *dev_priv = dev->dev_private;
- uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
uint32_t flush_domains = 0;
RING_LOCALS;
- /* The sampler always gets flushed on i965 (sigh) */
- if (IS_I965G(dev))
- flush_domains |= I915_GEM_DOMAIN_SAMPLER;
- BEGIN_LP_RING(2);
- OUT_RING(cmd);
- OUT_RING(0); /* noop */
- ADVANCE_LP_RING();
+ if (HAS_PIPE_CONTROL(dev)) {
+ /* PIPE_CONTROL flushes sampler & vertex by default on 965*/
+ if (!(IS_G4X(dev) || IS_IRONLAKE(dev)))
+ flush_domains |= I915_GEM_DOMAIN_SAMPLER |
+ I915_GEM_DOMAIN_VERTEX ;
+ BEGIN_LP_RING(4);
+ OUT_RING(GFX_OP_PIPE_CONTROL);
+ OUT_RING(0); /* unused addr */
+ OUT_RING(0); /* unused data */
+ OUT_RING(0); /* unused data */
+ ADVANCE_LP_RING();
+ } else {
+ BEGIN_LP_RING(2);
+ OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH);
+ OUT_RING(0); /* noop */
+ ADVANCE_LP_RING();
+ }
return flush_domains;
}
--
1.7.0.1
next prev parent reply other threads:[~2010-04-21 18:38 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-04-21 18:39 Use PIPE_CONTROL where possible Jesse Barnes
2010-04-21 18:39 ` [PATCH 1/5] drm/i915: cleanup FBC buffers at unload time Jesse Barnes
2010-04-21 18:39 ` [PATCH 2/5] drm/i915: use PIPE_CONTROL instruction on Ironlake and Sandy Bridge Jesse Barnes
2010-04-21 18:39 ` Jesse Barnes [this message]
2010-04-29 21:26 ` [PATCH 3/5] drm/i915: use PIPE_CONTROL to retire commands Eric Anholt
2010-05-03 19:41 ` Jesse Barnes
2010-04-21 18:39 ` [PATCH 4/5] drm/i915: use PIPE_CONTROL for GEM domain flushing Jesse Barnes
2010-04-21 18:39 ` [PATCH 5/5] drm/i915: enable PIPE_CONTROL on all 965 class chips Jesse Barnes
2010-04-21 19:49 ` [PATCH] drm/i915: avoid unnecessary PIPE_CONTROL flushing on non-Ironlake Jesse Barnes
2010-04-21 20:02 ` [PATCH] drm/i915: remove unnecessary PIPE_CONTROL cache flushing Jesse Barnes
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