From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH] drm/i915/edp: Flush the write before waiting for PLLs
Date: Fri, 6 Aug 2010 15:11:07 +0100 [thread overview]
Message-ID: <1281103867-8982-1-git-send-email-chris@chris-wilson.co.uk> (raw)
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/intel_display.c | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9814182..5cae58a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1570,6 +1570,7 @@ static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
dpa_ctl = I915_READ(DP_A);
dpa_ctl |= DP_PLL_ENABLE;
I915_WRITE(DP_A, dpa_ctl);
+ POSTING_READ(DP_A);
udelay(200);
}
--
1.7.1
reply other threads:[~2010-08-06 14:11 UTC|newest]
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