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From: Jesse Barnes <jbarnes@virtuousgeek.org>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 1/5] drm/i915: add panel reset workaround
Date: Fri, 13 Aug 2010 16:03:51 -0700	[thread overview]
Message-ID: <1281740635-3016-2-git-send-email-jbarnes@virtuousgeek.org> (raw)
In-Reply-To: <1281740635-3016-1-git-send-email-jbarnes@virtuousgeek.org>

Ironlake requires that we clear the reset panel bit during power
sequences and restore it afterwards.  Uncondtionally add code to do that
since it should be harmless on SNB+.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_dp.c |   17 ++++++++++++++++-
 1 files changed, 16 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 5dde80f..048e6a0 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -728,6 +728,12 @@ static void ironlake_edp_panel_on (struct drm_device *dev)
 		return;
 
 	pp = I915_READ(PCH_PP_CONTROL);
+
+	/* ILK workaround: disable reset around power sequence */
+	pp &= ~PANEL_POWER_RESET;
+	I915_WRITE(PCH_PP_CONTROL, pp);
+	POSTING_READ(PCH_PP_CONTROL);
+
 	pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON;
 	I915_WRITE(PCH_PP_CONTROL, pp);
 	do {
@@ -738,7 +744,9 @@ static void ironlake_edp_panel_on (struct drm_device *dev)
 		DRM_DEBUG_KMS("panel on wait timed out: 0x%08x\n", pp_status);
 
 	pp &= ~(PANEL_UNLOCK_REGS | EDP_FORCE_VDD);
+	pp |= PANEL_POWER_RESET; /* restore panel reset bit */
 	I915_WRITE(PCH_PP_CONTROL, pp);
+	POSTING_READ(PCH_PP_CONTROL);
 }
 
 static void ironlake_edp_panel_off (struct drm_device *dev)
@@ -748,6 +756,12 @@ static void ironlake_edp_panel_off (struct drm_device *dev)
 	u32 pp, pp_status;
 
 	pp = I915_READ(PCH_PP_CONTROL);
+
+	/* ILK workaround: disable reset around power sequence */
+	pp &= ~PANEL_POWER_RESET;
+	I915_WRITE(PCH_PP_CONTROL, pp);
+	POSTING_READ(PCH_PP_CONTROL);
+
 	pp &= ~POWER_TARGET_ON;
 	I915_WRITE(PCH_PP_CONTROL, pp);
 	do {
@@ -758,8 +772,9 @@ static void ironlake_edp_panel_off (struct drm_device *dev)
 		DRM_DEBUG_KMS("panel off wait timed out\n");
 
 	/* Make sure VDD is enabled so DP AUX will work */
-	pp |= EDP_FORCE_VDD;
+	pp |= EDP_FORCE_VDD | PANEL_POWER_RESET; /* restore panel reset bit */
 	I915_WRITE(PCH_PP_CONTROL, pp);
+	POSTING_READ(PCH_PP_CONTROL);
 }
 
 static void ironlake_edp_backlight_on (struct drm_device *dev)
-- 
1.7.0.4

  reply	other threads:[~2010-08-13 23:04 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-08-13 23:03 eDP mode setting fixes Jesse Barnes
2010-08-13 23:03 ` Jesse Barnes [this message]
2010-08-13 23:03 ` [PATCH 2/5] drm/i915: eDP mode set sequence corrections Jesse Barnes
2010-08-13 23:03 ` [PATCH 3/5] drm/i915: fix VGA plane disable for Ironlake+ Jesse Barnes
2010-08-16 14:13   ` Adam Jackson
2010-08-13 23:03 ` [PATCH 4/5] drm/i915: make sure eDP PLL is enabled at the right time Jesse Barnes
2010-08-13 23:03 ` [PATCH 5/5] drm/i915: add MMIO debug output Jesse Barnes

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