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From: Jesse Barnes <jbarnes@virtuousgeek.org>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 5/5] drm/i915: add MMIO debug output
Date: Fri, 13 Aug 2010 16:03:55 -0700	[thread overview]
Message-ID: <1281740635-3016-6-git-send-email-jbarnes@virtuousgeek.org> (raw)
In-Reply-To: <1281740635-3016-1-git-send-email-jbarnes@virtuousgeek.org>

Useful for capturing register read/write traces to send to the hw guys.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.h |   30 ++++++++++++++++++++++++++++--
 1 files changed, 28 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2e1744d..8bd566f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -256,6 +256,9 @@ typedef struct drm_i915_private {
 	int front_offset;
 	int current_page;
 	int page_flipping;
+#define I915_DEBUG_READ (1<<0)
+#define I915_DEBUG_WRITE (1<<1)
+	unsigned long debug_flags;
 
 	wait_queue_head_t irq_queue;
 	atomic_t irq_received;
@@ -1065,8 +1068,26 @@ extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
 		LOCK_TEST_WITH_RETURN(dev, file_priv);			\
 } while (0)
 
-#define I915_READ(reg)          readl(dev_priv->regs + (reg))
-#define I915_WRITE(reg, val)     writel(val, dev_priv->regs + (reg))
+static inline u32 i915_read(struct drm_i915_private *dev_priv, u32 reg)
+{
+	u32 val;
+
+	val = readl(dev_priv->regs + reg);
+	if (dev_priv->debug_flags & I915_DEBUG_READ)
+		printk(KERN_ERR "read 0x%08x from 0x%08x\n", val, reg);
+	return val;
+}
+
+static inline void i915_write(struct drm_i915_private *dev_priv, u32 reg,
+			      u32 val)
+{
+	writel(val, dev_priv->regs + reg);
+	if (dev_priv->debug_flags & I915_DEBUG_WRITE)
+		printk(KERN_ERR "wrote 0x%08x to 0x%08x\n", val, reg);
+}
+
+#define I915_READ(reg)          i915_read(dev_priv, (reg))
+#define I915_WRITE(reg, val)    i915_write(dev_priv, (reg), (val))
 #define I915_READ16(reg)	readw(dev_priv->regs + (reg))
 #define I915_WRITE16(reg, val)	writel(val, dev_priv->regs + (reg))
 #define I915_READ8(reg)		readb(dev_priv->regs + (reg))
@@ -1076,6 +1097,11 @@ extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
 #define POSTING_READ(reg)	(void)I915_READ(reg)
 #define POSTING_READ16(reg)	(void)I915_READ16(reg)
 
+#define I915_DEBUG_ENABLE_IO() (dev_priv->debug_flags |= I915_DEBUG_READ | \
+				I915_DEBUG_WRITE)
+#define I915_DEBUG_DISABLE_IO() (dev_priv->debug_flags &= ~(I915_DEBUG_READ | \
+							    I915_DEBUG_WRITE))
+
 #define I915_VERBOSE 0
 
 #define BEGIN_LP_RING(n)  do { \
-- 
1.7.0.4

      parent reply	other threads:[~2010-08-13 23:04 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-08-13 23:03 eDP mode setting fixes Jesse Barnes
2010-08-13 23:03 ` [PATCH 1/5] drm/i915: add panel reset workaround Jesse Barnes
2010-08-13 23:03 ` [PATCH 2/5] drm/i915: eDP mode set sequence corrections Jesse Barnes
2010-08-13 23:03 ` [PATCH 3/5] drm/i915: fix VGA plane disable for Ironlake+ Jesse Barnes
2010-08-16 14:13   ` Adam Jackson
2010-08-13 23:03 ` [PATCH 4/5] drm/i915: make sure eDP PLL is enabled at the right time Jesse Barnes
2010-08-13 23:03 ` Jesse Barnes [this message]

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