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From: Jesse Barnes <jbarnes@virtuousgeek.org>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 18/20] drm/i915/dp: don't bother with DP PLL for PCH attached eDP
Date: Thu,  7 Oct 2010 16:01:23 -0700	[thread overview]
Message-ID: <1286492485-18145-19-git-send-email-jbarnes@virtuousgeek.org> (raw)
In-Reply-To: <1286492485-18145-1-git-send-email-jbarnes@virtuousgeek.org>

We don't use the CPU DP PLL with PCH attached eDP panels, so don't
bother to enable it.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_dp.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index fa24d94..19e0d65 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -775,7 +775,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 	if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
 		intel_dp->DP |= DP_PIPEB_SELECT;
 
-	if (is_edp(intel_dp)) {
+	if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
 		/* don't miss out required setting for eDP */
 		intel_dp->DP |= DP_PLL_ENABLE;
 		if (adjusted_mode->clock < 200000)
-- 
1.7.0.4

  parent reply	other threads:[~2010-10-07 23:39 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-10-07 23:01 PCH eDP fixes Jesse Barnes
2010-10-07 23:01 ` [PATCH 01/20] drm/i915/dp: convert eDP checks to functions and document Jesse Barnes
2010-10-07 23:01 ` [PATCH 02/20] drm/i915/dp: remove redundant is_pch_edp checks Jesse Barnes
2010-10-07 23:01 ` [PATCH 03/20] drm/i915/dp: correct eDP lane count and bpp Jesse Barnes
2010-10-07 23:01 ` [PATCH 04/20] drm/i915: add eDP checking functions for the display code Jesse Barnes
2010-10-07 23:01 ` [PATCH 05/20] drm/i915: remove broken intel_pch_has_edp function Jesse Barnes
2010-10-07 23:01 ` [PATCH 06/20] drm/i915: fix CPU vs PCH eDP confusion Jesse Barnes
2010-10-07 23:01 ` [PATCH 07/20] drm/i915/dp: eDP power sequencing fixes Jesse Barnes
2010-10-07 23:01 ` [PATCH 08/20] drm/i915: add _DSM support Jesse Barnes
2010-10-07 23:01 ` [PATCH 09/20] drm/i915: fetch eDP configuration data from the VBT Jesse Barnes
2010-10-07 23:01 ` [PATCH 10/20] drm/i915: add Ironlake clock gating workaround for FDI link training Jesse Barnes
2010-10-07 23:01 ` [PATCH 11/20] drm/i915: fix PCH eDP SSC support Jesse Barnes
2010-10-07 23:01 ` [PATCH 12/20] drm/i915: use 120MHz refclk in PCH eDP case too Jesse Barnes
2010-10-07 23:01 ` [PATCH 13/20] drm/i915: use DPLL_DVO_HIGH_SPEED for PCH eDP Jesse Barnes
2010-10-07 23:01 ` [PATCH 14/20] drm/i915: fix ironlake CRTC enable/disable Jesse Barnes
2010-10-07 23:01 ` [PATCH 15/20] drm/i915: don't program FDI RX/TX in mode_set Jesse Barnes
2010-10-07 23:01 ` [PATCH 16/20] drm/i915/dp: cache eDP DPCD data Jesse Barnes
2010-10-07 23:01 ` [PATCH 17/20] drm/i915/dp: use VBT provided eDP params if available Jesse Barnes
2010-10-07 23:01 ` Jesse Barnes [this message]
2010-10-07 23:01 ` [PATCH 19/20] drm/i915/dp: make eDP PLL functions work as advertised Jesse Barnes
2010-10-07 23:01 ` [PATCH 20/20] drm/i915: diasable clock gating for the panel power sequencer Jesse Barnes
2010-10-08  9:50 ` PCH eDP fixes Jim Gettys
2010-10-08 10:00 ` Chris Wilson
2010-10-08 16:24   ` Jesse Barnes

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