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From: Zhenyu Wang <zhenyuw@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH -next 1/2] drm/i915: restore FDI link rate on sandybridge
Date: Wed, 13 Oct 2010 16:40:11 +0800	[thread overview]
Message-ID: <1286959212-2151-1-git-send-email-zhenyuw@linux.intel.com> (raw)

FDI_PLL_BIOS_0 register is for Ironlake only, don't apply to Sandybridge.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8e98d70..b711e98 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3709,7 +3709,10 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
 			 * Hence the bw of each lane in terms of the mode signal
 			 * is:
 			 */
-			link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
+			if (IS_GEN5(dev))
+				link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
+			else
+				link_bw = 270000;
 		}
 
 		/* determine panel color depth */
-- 
1.7.0.4

             reply	other threads:[~2010-10-13  8:39 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-10-13  8:40 Zhenyu Wang [this message]
2010-10-13  8:40 ` [PATCH -next 2/2] drm/i915: Fix GPIO pin to register mapping Zhenyu Wang
2010-10-13 16:00 ` [PATCH -next 1/2] drm/i915: restore FDI link rate on sandybridge Jesse Barnes
2010-10-13 16:32   ` Chris Wilson
2010-10-14  0:41   ` Zhenyu Wang

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