All of lore.kernel.org
 help / color / mirror / Atom feed
From: Mike Frysinger <vapier-aBrp7R+bbdUdnm+yROfE0A@public.gmane.org>
To: spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org,
	David Brownell
	<dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org>,
	Grant Likely
	<grant.likely-s3s/WqlpOiPyB63q8FvJNQ@public.gmane.org>
Cc: uclinux-dist-devel-ZG0+EudsQA8dtHy/vicBwGD2FQJk+8+b@public.gmane.org
Subject: [PATCH 06/28] Blackfin SPI: drop custom cs_change_per_word support
Date: Sun, 17 Oct 2010 18:59:19 -0400	[thread overview]
Message-ID: <1287356381-31495-7-git-send-email-vapier@gentoo.org> (raw)
In-Reply-To: <1287356381-31495-1-git-send-email-vapier-aBrp7R+bbdUdnm+yROfE0A@public.gmane.org>

As David points out, the cs_change_per_word option isn't standard, nor is
anyone actually using it.  So punt all of the dead code considering it
makes up ~10% of the code size.

Reported-by: David Brownell <dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org>
Signed-off-by: Mike Frysinger <vapier-aBrp7R+bbdUdnm+yROfE0A@public.gmane.org>
---
 arch/blackfin/include/asm/bfin5xx_spi.h |    1 -
 drivers/spi/spi_bfin5xx.c               |  148 +++----------------------------
 2 files changed, 12 insertions(+), 137 deletions(-)

diff --git a/arch/blackfin/include/asm/bfin5xx_spi.h b/arch/blackfin/include/asm/bfin5xx_spi.h
index ed4f8c6..ee3ecb9 100644
--- a/arch/blackfin/include/asm/bfin5xx_spi.h
+++ b/arch/blackfin/include/asm/bfin5xx_spi.h
@@ -120,7 +120,6 @@ struct bfin5xx_spi_chip {
 	u16 ctl_reg;
 	u8 enable_dma;
 	u8 bits_per_word;
-	u8 cs_change_per_word;
 	u16 cs_chg_udelay; /* Some devices require 16-bit delays */
 	u32 cs_gpio;
 	/* Value to send if no TX value is supplied, usually 0x0 or 0xFFFF */
diff --git a/drivers/spi/spi_bfin5xx.c b/drivers/spi/spi_bfin5xx.c
index 6150a8c..f4023a7 100644
--- a/drivers/spi/spi_bfin5xx.c
+++ b/drivers/spi/spi_bfin5xx.c
@@ -114,7 +114,6 @@ struct chip_data {
 	u8 width;		/* 0 or 1 */
 	u8 enable_dma;
 	u8 bits_per_word;	/* 8 or 16 */
-	u8 cs_change_per_word;
 	u16 cs_chg_udelay;	/* Some devices require > 255usec delay */
 	u32 cs_gpio;
 	u16 idle_tx_val;
@@ -309,24 +308,6 @@ static void bfin_spi_u8_writer(struct driver_data *drv_data)
 	}
 }
 
-static void bfin_spi_u8_cs_chg_writer(struct driver_data *drv_data)
-{
-	struct chip_data *chip = drv_data->cur_chip;
-
-	/* clear RXS (we check for RXS inside the loop) */
-	bfin_spi_dummy_read(drv_data);
-
-	while (drv_data->tx < drv_data->tx_end) {
-		bfin_spi_cs_active(drv_data, chip);
-		write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
-		/* make sure transfer finished before deactiving CS */
-		while (!(read_STAT(drv_data) & BIT_STAT_RXS))
-			cpu_relax();
-		bfin_spi_dummy_read(drv_data);
-		bfin_spi_cs_deactive(drv_data, chip);
-	}
-}
-
 static void bfin_spi_u8_reader(struct driver_data *drv_data)
 {
 	u16 tx_val = drv_data->cur_chip->idle_tx_val;
@@ -342,24 +323,6 @@ static void bfin_spi_u8_reader(struct driver_data *drv_data)
 	}
 }
 
-static void bfin_spi_u8_cs_chg_reader(struct driver_data *drv_data)
-{
-	struct chip_data *chip = drv_data->cur_chip;
-	u16 tx_val = chip->idle_tx_val;
-
-	/* discard old RX data and clear RXS */
-	bfin_spi_dummy_read(drv_data);
-
-	while (drv_data->rx < drv_data->rx_end) {
-		bfin_spi_cs_active(drv_data, chip);
-		write_TDBR(drv_data, tx_val);
-		while (!(read_STAT(drv_data) & BIT_STAT_RXS))
-			cpu_relax();
-		*(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
-		bfin_spi_cs_deactive(drv_data, chip);
-	}
-}
-
 static void bfin_spi_u8_duplex(struct driver_data *drv_data)
 {
 	/* discard old RX data and clear RXS */
@@ -373,23 +336,6 @@ static void bfin_spi_u8_duplex(struct driver_data *drv_data)
 	}
 }
 
-static void bfin_spi_u8_cs_chg_duplex(struct driver_data *drv_data)
-{
-	struct chip_data *chip = drv_data->cur_chip;
-
-	/* discard old RX data and clear RXS */
-	bfin_spi_dummy_read(drv_data);
-
-	while (drv_data->rx < drv_data->rx_end) {
-		bfin_spi_cs_active(drv_data, chip);
-		write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
-		while (!(read_STAT(drv_data) & BIT_STAT_RXS))
-			cpu_relax();
-		*(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
-		bfin_spi_cs_deactive(drv_data, chip);
-	}
-}
-
 static void bfin_spi_u16_writer(struct driver_data *drv_data)
 {
 	/* clear RXS (we check for RXS inside the loop) */
@@ -407,25 +353,6 @@ static void bfin_spi_u16_writer(struct driver_data *drv_data)
 	}
 }
 
-static void bfin_spi_u16_cs_chg_writer(struct driver_data *drv_data)
-{
-	struct chip_data *chip = drv_data->cur_chip;
-
-	/* clear RXS (we check for RXS inside the loop) */
-	bfin_spi_dummy_read(drv_data);
-
-	while (drv_data->tx < drv_data->tx_end) {
-		bfin_spi_cs_active(drv_data, chip);
-		write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
-		drv_data->tx += 2;
-		/* make sure transfer finished before deactiving CS */
-		while (!(read_STAT(drv_data) & BIT_STAT_RXS))
-			cpu_relax();
-		bfin_spi_dummy_read(drv_data);
-		bfin_spi_cs_deactive(drv_data, chip);
-	}
-}
-
 static void bfin_spi_u16_reader(struct driver_data *drv_data)
 {
 	u16 tx_val = drv_data->cur_chip->idle_tx_val;
@@ -442,25 +369,6 @@ static void bfin_spi_u16_reader(struct driver_data *drv_data)
 	}
 }
 
-static void bfin_spi_u16_cs_chg_reader(struct driver_data *drv_data)
-{
-	struct chip_data *chip = drv_data->cur_chip;
-	u16 tx_val = chip->idle_tx_val;
-
-	/* discard old RX data and clear RXS */
-	bfin_spi_dummy_read(drv_data);
-
-	while (drv_data->rx < drv_data->rx_end) {
-		bfin_spi_cs_active(drv_data, chip);
-		write_TDBR(drv_data, tx_val);
-		while (!(read_STAT(drv_data) & BIT_STAT_RXS))
-			cpu_relax();
-		*(u16 *) (drv_data->rx) = read_RDBR(drv_data);
-		drv_data->rx += 2;
-		bfin_spi_cs_deactive(drv_data, chip);
-	}
-}
-
 static void bfin_spi_u16_duplex(struct driver_data *drv_data)
 {
 	/* discard old RX data and clear RXS */
@@ -476,25 +384,6 @@ static void bfin_spi_u16_duplex(struct driver_data *drv_data)
 	}
 }
 
-static void bfin_spi_u16_cs_chg_duplex(struct driver_data *drv_data)
-{
-	struct chip_data *chip = drv_data->cur_chip;
-
-	/* discard old RX data and clear RXS */
-	bfin_spi_dummy_read(drv_data);
-
-	while (drv_data->rx < drv_data->rx_end) {
-		bfin_spi_cs_active(drv_data, chip);
-		write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
-		drv_data->tx += 2;
-		while (!(read_STAT(drv_data) & BIT_STAT_RXS))
-			cpu_relax();
-		*(u16 *) (drv_data->rx) = read_RDBR(drv_data);
-		drv_data->rx += 2;
-		bfin_spi_cs_deactive(drv_data, chip);
-	}
-}
-
 /* test if ther is more transfer to be done */
 static void *bfin_spi_next_transfer(struct driver_data *drv_data)
 {
@@ -773,23 +662,17 @@ static void bfin_spi_pump_transfers(unsigned long data)
 	case 8:
 		drv_data->n_bytes = 1;
 		width = CFG_SPI_WORDSIZE8;
-		drv_data->read = chip->cs_change_per_word ?
-			bfin_spi_u8_cs_chg_reader : bfin_spi_u8_reader;
-		drv_data->write = chip->cs_change_per_word ?
-			bfin_spi_u8_cs_chg_writer : bfin_spi_u8_writer;
-		drv_data->duplex = chip->cs_change_per_word ?
-			bfin_spi_u8_cs_chg_duplex : bfin_spi_u8_duplex;
+		drv_data->read = bfin_spi_u8_reader;
+		drv_data->write = bfin_spi_u8_writer;
+		drv_data->duplex = bfin_spi_u8_duplex;
 		break;
 
 	case 16:
 		drv_data->n_bytes = 2;
 		width = CFG_SPI_WORDSIZE16;
-		drv_data->read = chip->cs_change_per_word ?
-			bfin_spi_u16_cs_chg_reader : bfin_spi_u16_reader;
-		drv_data->write = chip->cs_change_per_word ?
-			bfin_spi_u16_cs_chg_writer : bfin_spi_u16_writer;
-		drv_data->duplex = chip->cs_change_per_word ?
-			bfin_spi_u16_cs_chg_duplex : bfin_spi_u16_duplex;
+		drv_data->read = bfin_spi_u16_reader;
+		drv_data->write = bfin_spi_u16_writer;
+		drv_data->duplex = bfin_spi_u16_duplex;
 		break;
 
 	default:
@@ -1164,7 +1047,6 @@ static int bfin_spi_setup(struct spi_device *spi)
 		    && drv_data->master_info->enable_dma;
 		chip->ctl_reg = chip_info->ctl_reg;
 		chip->bits_per_word = chip_info->bits_per_word;
-		chip->cs_change_per_word = chip_info->cs_change_per_word;
 		chip->cs_chg_udelay = chip_info->cs_chg_udelay;
 		chip->cs_gpio = chip_info->cs_gpio;
 		chip->idle_tx_val = chip_info->idle_tx_val;
@@ -1193,23 +1075,17 @@ static int bfin_spi_setup(struct spi_device *spi)
 	case 8:
 		chip->n_bytes = 1;
 		chip->width = CFG_SPI_WORDSIZE8;
-		chip->read = chip->cs_change_per_word ?
-			bfin_spi_u8_cs_chg_reader : bfin_spi_u8_reader;
-		chip->write = chip->cs_change_per_word ?
-			bfin_spi_u8_cs_chg_writer : bfin_spi_u8_writer;
-		chip->duplex = chip->cs_change_per_word ?
-			bfin_spi_u8_cs_chg_duplex : bfin_spi_u8_duplex;
+		chip->read = bfin_spi_u8_reader;
+		chip->write = bfin_spi_u8_writer;
+		chip->duplex = bfin_spi_u8_duplex;
 		break;
 
 	case 16:
 		chip->n_bytes = 2;
 		chip->width = CFG_SPI_WORDSIZE16;
-		chip->read = chip->cs_change_per_word ?
-			bfin_spi_u16_cs_chg_reader : bfin_spi_u16_reader;
-		chip->write = chip->cs_change_per_word ?
-			bfin_spi_u16_cs_chg_writer : bfin_spi_u16_writer;
-		chip->duplex = chip->cs_change_per_word ?
-			bfin_spi_u16_cs_chg_duplex : bfin_spi_u16_duplex;
+		chip->read = bfin_spi_u16_reader;
+		chip->write = bfin_spi_u16_writer;
+		chip->duplex = bfin_spi_u16_duplex;
 		break;
 
 	default:
-- 
1.7.3.1

  parent reply	other threads:[~2010-10-17 22:59 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-10-17 22:59 [PATCH 00/28] Blackfin SPI updates for 2.6.36 Mike Frysinger
     [not found] ` <1287356381-31495-1-git-send-email-vapier-aBrp7R+bbdUdnm+yROfE0A@public.gmane.org>
2010-10-17 22:59   ` [PATCH 01/28] Blackfin SPI: fix resources leakage Mike Frysinger
2010-10-17 22:59   ` [PATCH 02/28] Blackfin SPI: work around anomaly 05000119 Mike Frysinger
2010-10-17 22:59   ` [PATCH 03/28] Blackfin SPI: force sane master-mode state at boot Mike Frysinger
2010-10-17 22:59   ` [PATCH 04/28] Blackfin SPI: utilize the SPI interrupt in PIO mode Mike Frysinger
2010-10-17 22:59   ` [PATCH 05/28] Blackfin SPI: fix CS handling Mike Frysinger
2010-10-17 22:59   ` Mike Frysinger [this message]
2010-10-17 22:59   ` [PATCH 07/28] Blackfin SPI: punt useless null read/write funcs Mike Frysinger
2010-10-17 22:59   ` [PATCH 08/28] Blackfin SPI: fix up some unused/misleading comments Mike Frysinger
2010-10-17 22:59   ` [PATCH 09/28] Blackfin SPI: convert queue run state to true/false Mike Frysinger
2010-10-17 22:59   ` [PATCH 10/28] Blackfin SPI: convert read/write/duplex funcs to a dedicated ops structure Mike Frysinger
2010-10-17 22:59   ` [PATCH 11/28] Blackfin SPI: convert struct names to something more logical Mike Frysinger
     [not found]     ` <1287356381-31495-12-git-send-email-vapier-aBrp7R+bbdUdnm+yROfE0A@public.gmane.org>
2010-10-18  6:02       ` Grant Likely
     [not found]         ` <20101018060253.GA19399-MrY2KI0G/OVr83L8+7iqerDks+cytr/Z@public.gmane.org>
2010-10-18  6:10           ` Mike Frysinger
     [not found]             ` <AANLkTimJtoRWL0auw1xHthXbkBc6L2b1ph18WZA+_PdY-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2010-10-18  6:20               ` Grant Likely
     [not found]                 ` <20101018062025.GD19399-MrY2KI0G/OVr83L8+7iqerDks+cytr/Z@public.gmane.org>
2010-10-18  6:28                   ` Mike Frysinger
     [not found]                     ` <AANLkTi=pBYVLCYVtwd3L=O31O4FxOPwQLJQK5WUkdRS9-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2010-10-18  6:31                       ` Grant Likely
2010-10-17 22:59   ` [PATCH 12/28] Blackfin SPI: drop extra memory we don't need Mike Frysinger
2010-10-17 22:59   ` [PATCH 13/28] Blackfin SPI: use the SPI namespaced bit names Mike Frysinger
2010-10-17 22:59   ` [PATCH 14/28] Blackfin: SPI: expand SPI bitmasks Mike Frysinger
     [not found]     ` <1287356381-31495-15-git-send-email-vapier-aBrp7R+bbdUdnm+yROfE0A@public.gmane.org>
2010-10-18  6:04       ` Grant Likely
     [not found]         ` <20101018060416.GB19399-MrY2KI0G/OVr83L8+7iqerDks+cytr/Z@public.gmane.org>
2010-10-18  6:11           ` Mike Frysinger
2010-10-17 22:59   ` [PATCH 15/28] Blackfin SPI: redo GPIO CS handling Mike Frysinger
2010-10-17 22:59   ` [PATCH 16/28] Blackfin SPI: save/restore state when suspending/resuming Mike Frysinger
2010-10-17 22:59   ` [PATCH 17/28] Blackfin SPI: sync hardware state before reprogramming everything Mike Frysinger
2010-10-17 22:59   ` [PATCH 18/28] Blackfin SPI: use nosync when disabling the IRQ from the IRQ handler Mike Frysinger
2010-10-17 22:59   ` [PATCH 19/28] Blackfin SPI: push all size checks into the transfer function Mike Frysinger
2010-10-17 22:59   ` [PATCH 20/28] Blackfin SPI: reset ctl_reg bits when setup is run again on a device Mike Frysinger
2010-10-17 22:59   ` [PATCH 21/28] Blackfin SPI: combine duplicate SPI_CTL read/write logic Mike Frysinger
2010-10-17 22:59   ` [PATCH 22/28] Blackfin SPI: use dma_disable_irq_nosync() in irq handler Mike Frysinger
2010-10-17 22:59   ` [PATCH 23/28] Blackfin SPI: reject unsupported SPI modes Mike Frysinger
2010-10-17 22:59   ` [PATCH 24/28] Blackfin SPI: fix typo in comment Mike Frysinger
2010-10-17 22:59   ` [PATCH 25/28] Blackfin SPI: cs should be always low when a new transfer begins Mike Frysinger
2010-10-17 22:59   ` [PATCH 26/28] Blackfin SPI: warn when CS is driven by hardware (CPHA=0) Mike Frysinger
2010-10-17 22:59   ` [PATCH 27/28] Blackfin SPI: check per-transfer bits_per_word Mike Frysinger
2010-10-17 22:59   ` [PATCH 28/28] Blackfin SPI: init early Mike Frysinger
     [not found]     ` <1287356381-31495-29-git-send-email-vapier-aBrp7R+bbdUdnm+yROfE0A@public.gmane.org>
2010-10-18  6:12       ` Grant Likely
     [not found]         ` <20101018061211.GC19399-MrY2KI0G/OVr83L8+7iqerDks+cytr/Z@public.gmane.org>
2010-10-18  6:14           ` Mike Frysinger
     [not found]             ` <AANLkTi=AwuK8-U8+Ezm1JVrvD1Taqwq53EzahA5Ag4Uf-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2010-10-18  6:21               ` Grant Likely
2010-10-18  6:28   ` [PATCH 00/28] Blackfin SPI updates for 2.6.36 Grant Likely
     [not found]     ` <20101018062834.GG19399-MrY2KI0G/OVr83L8+7iqerDks+cytr/Z@public.gmane.org>
2010-10-18  6:34       ` Mike Frysinger
     [not found]         ` <AANLkTims9Z+XGXMdcAH53OBO=S9aYiszxHczmsTn06Gd-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2010-10-18  6:37           ` Mike Frysinger
     [not found]             ` <AANLkTim1p0Ukufh1dWGSk8L2yA4xwQzsWmr8EK_AbfLP-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2010-10-18  6:49               ` Grant Likely
2010-10-18  6:49           ` Mike Frysinger
     [not found]             ` <AANLkTimmVQ0EtkACtXqxO0vkXfN9FoyF9c6OLo3JNPUC-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2010-10-18  7:04               ` Grant Likely
     [not found]                 ` <AANLkTimE33PngPfSBkQDVR7x6H8fMNQ9z3sXNC9KZPWf-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2010-10-18 15:27                   ` Grant Likely
2010-10-18  6:46   ` [PATCH 29/28] spi/bfin_spi: namespace local structs Mike Frysinger

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1287356381-31495-7-git-send-email-vapier@gentoo.org \
    --to=vapier-abrp7r+bbdudnm+yrofe0a@public.gmane.org \
    --cc=dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org \
    --cc=grant.likely-s3s/WqlpOiPyB63q8FvJNQ@public.gmane.org \
    --cc=spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org \
    --cc=uclinux-dist-devel-ZG0+EudsQA8dtHy/vicBwGD2FQJk+8+b@public.gmane.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.