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From: Zou Nan hai <nanhai.zou@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH] enable BLT acceleate on gen6
Date: Fri, 29 Oct 2010 13:18:32 +0800	[thread overview]
Message-ID: <1288329512-1721-1-git-send-email-nanhai.zou@intel.com> (raw)

uxa:	enable BLT command on gen6,
	BLT command will goto BLT ring buffer
	on gen6.

Signed-off-by:Zou Nan hai <nanhai.zou@intel.com>
---
 src/i830_reg.h          |    2 +
 src/intel.h             |    4 +++
 src/intel_batchbuffer.c |   37 +++++++++++++++++++++---------
 src/intel_batchbuffer.h |   10 +++++++-
 src/intel_driver.c      |    2 -
 src/intel_uxa.c         |   56 ++++++++++++++++++++--------------------------
 6 files changed, 65 insertions(+), 46 deletions(-)

diff --git a/src/i830_reg.h b/src/i830_reg.h
index 4080896..93d03cf 100644
--- a/src/i830_reg.h
+++ b/src/i830_reg.h
@@ -32,6 +32,8 @@
 
 /* Flush */
 #define MI_FLUSH			(0x04<<23)
+#define MI_FLUSH_DW			(0x26<<23)
+
 #define MI_WRITE_DIRTY_STATE		(1<<4)
 #define MI_END_SCENE			(1<<3)
 #define MI_GLOBAL_SNAPSHOT_COUNT_RESET	(1<<3)
diff --git a/src/intel.h b/src/intel.h
index b74a061..26f4a18 100644
--- a/src/intel.h
+++ b/src/intel.h
@@ -276,6 +276,10 @@ typedef struct intel_screen_private {
 	unsigned char *MMIOBase;
 	int cpp;
 
+#define RENDER_BATCH			0
+#define BLT_BATCH			1	
+	unsigned int current_batch;
+
 	unsigned int bufferOffset;	/* for I830SelectBuffer */
 
 	/* These are set in PreInit and never changed. */
diff --git a/src/intel_batchbuffer.c b/src/intel_batchbuffer.c
index e7ca69d..584910b 100644
--- a/src/intel_batchbuffer.c
+++ b/src/intel_batchbuffer.c
@@ -147,14 +147,22 @@ void intel_batch_emit_flush(ScrnInfoPtr scrn)
 	assert (!intel->in_batch_atomic);
 
 	/* Big hammer, look to the pipelined flushes in future. */
-	flags = MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE;
-	if (INTEL_INFO(intel)->gen >= 40)
-		flags = 0;
-
-	BEGIN_BATCH(1);
-	OUT_BATCH(MI_FLUSH | flags);
-	ADVANCE_BATCH();
-
+	if (intel->current_batch == BLT_BATCH) {
+		BEGIN_BATCH_BLT(4);
+		OUT_BATCH(MI_FLUSH_DW | 2);
+		OUT_BATCH(0);
+		OUT_BATCH(0);
+		OUT_BATCH(0);
+		ADVANCE_BATCH();
+	} else {
+		flags = MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE;
+		if (INTEL_INFO(intel)->gen >= 40)
+			flags = 0;
+
+		BEGIN_BATCH(1);
+		OUT_BATCH(MI_FLUSH | flags);
+		ADVANCE_BATCH();
+	}
 	intel_batch_do_flush(scrn);
 }
 
@@ -190,9 +198,16 @@ void intel_batch_submit(ScrnInfoPtr scrn, int flush)
 	}
 
 	ret = dri_bo_subdata(intel->batch_bo, 0, intel->batch_used*4, intel->batch_ptr);
-	if (ret == 0)
-		ret = dri_bo_exec(intel->batch_bo, intel->batch_used*4,
-				  NULL, 0, 0xffffffff);
+	if (ret == 0) {
+		if (intel->current_batch == RENDER_BATCH)
+			ret = dri_bo_exec(intel->batch_bo, intel->batch_used*4,
+					NULL, 0, 0xffffffff);
+		else
+			ret = drm_intel_bo_mrb_exec(intel->batch_bo, 
+					intel->batch_used*4,
+					NULL, 0, 0xffffffff, I915_EXEC_BLT);
+	}
+
 	if (ret != 0) {
 		if (ret == -EIO) {
 			static int once;
diff --git a/src/intel_batchbuffer.h b/src/intel_batchbuffer.h
index bf7a5d9..607fb9b 100644
--- a/src/intel_batchbuffer.h
+++ b/src/intel_batchbuffer.h
@@ -63,7 +63,9 @@ static inline void intel_batch_start_atomic(ScrnInfoPtr scrn, unsigned int sz)
 	intel_screen_private *intel = intel_get_screen_private(scrn);
 
 	assert(!intel->in_batch_atomic);
+
 	intel_batch_require_space(scrn, intel, sz * 4);
+	intel->current_batch = RENDER_BATCH;				\
 
 	intel->in_batch_atomic = TRUE;
 	intel->batch_atomic_limit = intel->batch_used + sz;
@@ -173,17 +175,23 @@ union intfloat {
 	OUT_BATCH(tmp.ui);			\
 } while(0)
 
-#define BEGIN_BATCH(n)							\
+#define __BEGIN_BATCH(n,batch_idx)					\
 do {									\
 	if (intel->batch_emitting != 0)					\
 		FatalError("%s: BEGIN_BATCH called without closing "	\
 			   "ADVANCE_BATCH\n", __FUNCTION__);		\
 	assert(!intel->in_batch_atomic);				\
+	if (intel->current_batch != batch_idx)				\
+		intel_batch_submit(scrn, TRUE);				\
 	intel_batch_require_space(scrn, intel, (n) * 4);		\
+	intel->current_batch = batch_idx;				\
 	intel->batch_emitting = (n);					\
 	intel->batch_emit_start = intel->batch_used;			\
 } while (0)
 
+#define BEGIN_BATCH(n) 	__BEGIN_BATCH(n,RENDER_BATCH)
+#define BEGIN_BATCH_BLT(n) 	__BEGIN_BATCH(n,BLT_BATCH)
+
 #define ADVANCE_BATCH() do {						\
 	if (intel->batch_emitting == 0)					\
 		FatalError("%s: ADVANCE_BATCH called with no matching "	\
diff --git a/src/intel_driver.c b/src/intel_driver.c
index b16913b..160d08d 100644
--- a/src/intel_driver.c
+++ b/src/intel_driver.c
@@ -573,8 +573,6 @@ static Bool I830PreInit(ScrnInfoPtr scrn, int flags)
 	}
 
 	intel->use_shadow = FALSE;
-	if (IS_GEN6(intel))
-		intel->use_shadow = TRUE;
 
 	if (xf86IsOptionSet(intel->Options, OPTION_SHADOW)) {
 		intel->use_shadow =
diff --git a/src/intel_uxa.c b/src/intel_uxa.c
index 23679bc..6605e20 100644
--- a/src/intel_uxa.c
+++ b/src/intel_uxa.c
@@ -207,16 +207,9 @@ intel_uxa_pixmap_compute_size(PixmapPtr pixmap,
 }
 
 static Bool
-i830_uxa_check_solid(DrawablePtr drawable, int alu, Pixel planemask)
+intel_uxa_check_solid(DrawablePtr drawable, int alu, Pixel planemask)
 {
 	ScrnInfoPtr scrn = xf86Screens[drawable->pScreen->myNum];
-	intel_screen_private *intel = intel_get_screen_private(scrn);
-
-	if (IS_GEN6(intel)) {
-		intel_debug_fallback(scrn,
-				     "Sandybridge BLT engine not supported\n");
-		return FALSE;
-	}
 
 	if (!UXA_PM_IS_SOLID(drawable, planemask)) {
 		intel_debug_fallback(scrn, "planemask is not solid\n");
@@ -239,7 +232,7 @@ i830_uxa_check_solid(DrawablePtr drawable, int alu, Pixel planemask)
  * Sets up hardware state for a series of solid fills.
  */
 static Bool
-i830_uxa_prepare_solid(PixmapPtr pixmap, int alu, Pixel planemask, Pixel fg)
+intel_uxa_prepare_solid(PixmapPtr pixmap, int alu, Pixel planemask, Pixel fg)
 {
 	ScrnInfoPtr scrn = xf86Screens[pixmap->drawable.pScreen->myNum];
 	intel_screen_private *intel = intel_get_screen_private(scrn);
@@ -272,7 +265,7 @@ i830_uxa_prepare_solid(PixmapPtr pixmap, int alu, Pixel planemask, Pixel fg)
 	return TRUE;
 }
 
-static void i830_uxa_solid(PixmapPtr pixmap, int x1, int y1, int x2, int y2)
+static void intel_uxa_solid(PixmapPtr pixmap, int x1, int y1, int x2, int y2)
 {
 	ScrnInfoPtr scrn = xf86Screens[pixmap->drawable.pScreen->myNum];
 	intel_screen_private *intel = intel_get_screen_private(scrn);
@@ -294,7 +287,10 @@ static void i830_uxa_solid(PixmapPtr pixmap, int x1, int y1, int x2, int y2)
 	pitch = intel_pixmap_pitch(pixmap);
 
 	{
-		BEGIN_BATCH(6);
+		if (IS_GEN6(intel))
+			BEGIN_BATCH_BLT(6);
+		else
+			BEGIN_BATCH(6);
 
 		cmd = XY_COLOR_BLT_CMD;
 
@@ -322,7 +318,7 @@ static void i830_uxa_solid(PixmapPtr pixmap, int x1, int y1, int x2, int y2)
 	ironlake_blt_workaround(scrn);
 }
 
-static void i830_uxa_done_solid(PixmapPtr pixmap)
+static void intel_uxa_done_solid(PixmapPtr pixmap)
 {
 	ScrnInfoPtr scrn = xf86Screens[pixmap->drawable.pScreen->myNum];
 
@@ -334,17 +330,10 @@ static void i830_uxa_done_solid(PixmapPtr pixmap)
  *   - support planemask using FULL_BLT_CMD?
  */
 static Bool
-i830_uxa_check_copy(PixmapPtr source, PixmapPtr dest,
+intel_uxa_check_copy(PixmapPtr source, PixmapPtr dest,
 		    int alu, Pixel planemask)
 {
 	ScrnInfoPtr scrn = xf86Screens[dest->drawable.pScreen->myNum];
-	intel_screen_private *intel = intel_get_screen_private(scrn);
-
-	if (IS_GEN6(intel)) {
-		intel_debug_fallback(scrn,
-				     "Sandybridge BLT engine not supported\n");
-		return FALSE;
-	}
 
 	if (!UXA_PM_IS_SOLID(&source->drawable, planemask)) {
 		intel_debug_fallback(scrn, "planemask is not solid");
@@ -373,7 +362,7 @@ i830_uxa_check_copy(PixmapPtr source, PixmapPtr dest,
 }
 
 static Bool
-i830_uxa_prepare_copy(PixmapPtr source, PixmapPtr dest, int xdir,
+intel_uxa_prepare_copy(PixmapPtr source, PixmapPtr dest, int xdir,
 		      int ydir, int alu, Pixel planemask)
 {
 	ScrnInfoPtr scrn = xf86Screens[dest->drawable.pScreen->myNum];
@@ -405,7 +394,7 @@ i830_uxa_prepare_copy(PixmapPtr source, PixmapPtr dest, int xdir,
 }
 
 static void
-i830_uxa_copy(PixmapPtr dest, int src_x1, int src_y1, int dst_x1,
+intel_uxa_copy(PixmapPtr dest, int src_x1, int src_y1, int dst_x1,
 	      int dst_y1, int w, int h)
 {
 	ScrnInfoPtr scrn = xf86Screens[dest->drawable.pScreen->myNum];
@@ -448,7 +437,10 @@ i830_uxa_copy(PixmapPtr dest, int src_x1, int src_y1, int dst_x1,
 	src_pitch = intel_pixmap_pitch(intel->render_source);
 
 	{
-		BEGIN_BATCH(8);
+		if (IS_GEN6(intel))
+			BEGIN_BATCH_BLT(8);
+		else
+			BEGIN_BATCH(8);
 
 		cmd = XY_SRC_COPY_BLT_CMD;
 
@@ -491,7 +483,7 @@ i830_uxa_copy(PixmapPtr dest, int src_x1, int src_y1, int dst_x1,
 	ironlake_blt_workaround(scrn);
 }
 
-static void i830_uxa_done_copy(PixmapPtr dest)
+static void intel_uxa_done_copy(PixmapPtr dest)
 {
 	ScrnInfoPtr scrn = xf86Screens[dest->drawable.pScreen->myNum];
 
@@ -1186,16 +1178,16 @@ Bool intel_uxa_init(ScreenPtr screen)
 	intel->vertex_bo = NULL;
 
 	/* Solid fill */
-	intel->uxa_driver->check_solid = i830_uxa_check_solid;
-	intel->uxa_driver->prepare_solid = i830_uxa_prepare_solid;
-	intel->uxa_driver->solid = i830_uxa_solid;
-	intel->uxa_driver->done_solid = i830_uxa_done_solid;
+	intel->uxa_driver->check_solid = intel_uxa_check_solid;
+	intel->uxa_driver->prepare_solid = intel_uxa_prepare_solid;
+	intel->uxa_driver->solid = intel_uxa_solid;
+	intel->uxa_driver->done_solid = intel_uxa_done_solid;
 
 	/* Copy */
-	intel->uxa_driver->check_copy = i830_uxa_check_copy;
-	intel->uxa_driver->prepare_copy = i830_uxa_prepare_copy;
-	intel->uxa_driver->copy = i830_uxa_copy;
-	intel->uxa_driver->done_copy = i830_uxa_done_copy;
+	intel->uxa_driver->check_copy = intel_uxa_check_copy;
+	intel->uxa_driver->prepare_copy = intel_uxa_prepare_copy;
+	intel->uxa_driver->copy = intel_uxa_copy;
+	intel->uxa_driver->done_copy = intel_uxa_done_copy;
 
 	/* Composite */
 	if (IS_GEN2(intel)) {
-- 
1.7.1

             reply	other threads:[~2010-10-29  5:11 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-10-29  5:18 Zou Nan hai [this message]
2010-10-29  8:39 ` [PATCH] enable BLT acceleate on gen6 Chris Wilson
2010-10-29 19:13 ` Chris Wilson
2010-11-01  0:56   ` Zou, Nanhai
2010-11-01  3:33   ` Zou, Nanhai

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