From: Nishanth Menon <nm@ti.com>
To: linux-omap <linux-omap@vger.kernel.org>
Cc: Kevin <khilman@deeprootsystems.com>,
Jean Pihet <jean.pihet@newoldbits.com>,
Vishwanath Sripathy <vishwanath.bs@ti.com>,
Tony <tony@atomide.com>
Subject: [PATCH 01/13] OMAP3: PM: Update clean_l2 to use v7_flush_dcache_all
Date: Thu, 18 Nov 2010 19:54:46 -0600 [thread overview]
Message-ID: <1290131698-6194-2-git-send-email-nm@ti.com> (raw)
In-Reply-To: <1290131698-6194-1-git-send-email-nm@ti.com>
From: Richard Woodruff <r-woodruff2@ti.com>
Analysis in TI kernel with ETM showed that using cache mapped flush
in kernel instead of SO mapped flush cost drops by 65% (3.39mS down
to 1.17mS) for clean_l2 which is used during sleep sequences.
Overall:
- speed up
- unfortunately there isn't a good alternative flush method today
- code reduction and less maintenance and potential bug in
unmaintained code
This also fixes the bug with the clean_l2 function usage.
Reported-by: Tony Lindgren <tony@atomide.com>
[nm@ti.com: ported rkw's proposal to 2.6.37-rc2]
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Richard Woodruff <r-woodruff2@ti.com>
---
Side note: just dcache needs to be flushed based on inputs from TI internal team
arch/arm/mach-omap2/sleep34xx.S | 79 ++++++--------------------------------
1 files changed, 13 insertions(+), 66 deletions(-)
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 2fb205a..8f207b2 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -520,72 +520,17 @@ clean_caches:
cmp r9, #1 /* Check whether L2 inval is required or not*/
bne skip_l2_inval
clean_l2:
- /* read clidr */
- mrc p15, 1, r0, c0, c0, 1
- /* extract loc from clidr */
- ands r3, r0, #0x7000000
- /* left align loc bit field */
- mov r3, r3, lsr #23
- /* if loc is 0, then no need to clean */
- beq finished
- /* start clean at cache level 0 */
- mov r10, #0
-loop1:
- /* work out 3x current cache level */
- add r2, r10, r10, lsr #1
- /* extract cache type bits from clidr*/
- mov r1, r0, lsr r2
- /* mask of the bits for current cache only */
- and r1, r1, #7
- /* see what cache we have at this level */
- cmp r1, #2
- /* skip if no cache, or just i-cache */
- blt skip
- /* select current cache level in cssr */
- mcr p15, 2, r10, c0, c0, 0
- /* isb to sych the new cssr&csidr */
- isb
- /* read the new csidr */
- mrc p15, 1, r1, c0, c0, 0
- /* extract the length of the cache lines */
- and r2, r1, #7
- /* add 4 (line length offset) */
- add r2, r2, #4
- ldr r4, assoc_mask
- /* find maximum number on the way size */
- ands r4, r4, r1, lsr #3
- /* find bit position of way size increment */
- clz r5, r4
- ldr r7, numset_mask
- /* extract max number of the index size*/
- ands r7, r7, r1, lsr #13
-loop2:
- mov r9, r4
- /* create working copy of max way size*/
-loop3:
- /* factor way and cache number into r11 */
- orr r11, r10, r9, lsl r5
- /* factor index number into r11 */
- orr r11, r11, r7, lsl r2
- /*clean & invalidate by set/way */
- mcr p15, 0, r11, c7, c10, 2
- /* decrement the way*/
- subs r9, r9, #1
- bge loop3
- /*decrement the index */
- subs r7, r7, #1
- bge loop2
-skip:
- add r10, r10, #2
- /* increment cache number */
- cmp r3, r10
- bgt loop1
-finished:
- /*swith back to cache level 0 */
- mov r10, #0
- /* select current cache level in cssr */
- mcr p15, 2, r10, c0, c0, 0
- isb
+ /*
+ * jump out to kernel flush routine
+ * - resue that code is better
+ * - it executes in a cached space so is faster than refetch per-block
+ * - should be faster and will change with kernel
+ * - 'might' have to copy address, load and jump to it
+ */
+ ldr r1, kernel_flush
+ mov lr, pc
+ bx r1
+
skip_l2_inval:
/* Data memory barrier and Data sync barrier */
mov r1, #0
@@ -668,5 +613,7 @@ cache_pred_disable_mask:
.word 0xFFFFE7FB
control_stat:
.word CONTROL_STAT
+kernel_flush:
+ .word v7_flush_dcache_all
ENTRY(omap34xx_cpu_suspend_sz)
.word . - omap34xx_cpu_suspend
--
1.6.3.3
next prev parent reply other threads:[~2010-11-19 1:55 UTC|newest]
Thread overview: 63+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-11-19 1:54 [PATCH 00/13] OMAP3: OFF mode fixes Nishanth Menon
2010-11-19 1:54 ` Nishanth Menon [this message]
2010-11-19 9:46 ` [PATCH 01/13] OMAP3: PM: Update clean_l2 to use v7_flush_dcache_all Jean Pihet
2010-11-19 9:57 ` Peter 'p2' De Schrijver
2010-11-19 10:15 ` Jean Pihet
2010-11-19 1:54 ` [PATCH 02/13] OMAP3: PM: Errata i581 suppport: dll kick strategy Nishanth Menon
2010-11-24 16:51 ` Sripathy, Vishwanath
2010-11-24 17:24 ` Nishanth Menon
2010-11-25 6:39 ` Sripathy, Vishwanath
2010-11-25 12:22 ` Peter 'p2' De Schrijver
2010-11-19 1:54 ` [PATCH 03/13] OMAP3: PM: make secure ram save size configurable Nishanth Menon
2010-11-19 1:54 ` [PATCH 04/13] OMAP3: PM: Save secure RAM context before entering WFI Nishanth Menon
2010-11-19 1:54 ` [PATCH 05/13] OMAP3: PM: optional save secure RAM context every core off cycle Nishanth Menon
2010-11-19 1:54 ` [PATCH 06/13] OMAP3: PM: Fix secure save size for OMAP3 Nishanth Menon
2010-11-19 1:54 ` [PATCH 07/13] OMAP3: PM: allocate secure RAM context memory from low-mem Nishanth Menon
2010-11-19 1:54 ` [PATCH 08/13] OMAP3: PM: Deny MPU idle while saving secure RAM Nishanth Menon
2010-11-19 17:08 ` Kevin Hilman
2010-11-19 17:16 ` Nishanth Menon
2010-11-19 17:18 ` Santosh Shilimkar
2010-11-19 17:24 ` Nishanth Menon
2010-11-19 17:28 ` Santosh Shilimkar
2010-11-19 18:51 ` Nishanth Menon
2010-11-19 20:39 ` Kevin Hilman
2010-11-19 20:54 ` Nishanth Menon
2010-11-19 21:06 ` Kevin Hilman
2010-11-19 21:15 ` Nishanth Menon
2010-11-20 10:04 ` Santosh Shilimkar
2010-11-19 19:41 ` Kevin Hilman
2010-11-19 20:18 ` Nishanth Menon
2010-11-19 20:55 ` Kevin Hilman
2010-11-19 21:02 ` Nishanth Menon
2010-11-19 21:09 ` Kevin Hilman
2010-11-20 10:02 ` Santosh Shilimkar
2010-11-19 1:54 ` [PATCH 09/13] OMAP3: PM: Apply errata i540 before save secure ram Nishanth Menon
2010-11-19 10:09 ` Jean Pihet
2010-11-19 12:12 ` Nishanth Menon
2010-11-19 12:54 ` Jean Pihet
2010-11-19 17:15 ` Kevin Hilman
2010-11-19 17:18 ` Nishanth Menon
2010-11-19 19:47 ` Kevin Hilman
2010-11-19 20:08 ` Nishanth Menon
2010-11-19 1:54 ` [PATCH 10/13] OMAP3: PM: Errata i582: per domain reset issue: uart Nishanth Menon
2010-11-22 18:59 ` Kevin Hilman
2010-11-19 1:54 ` [PATCH 11/13] OMAP3630: PM: Errata i608: disable RTA Nishanth Menon
2010-11-19 9:57 ` Jean Pihet
2010-11-19 12:09 ` Nishanth Menon
2010-11-19 1:54 ` [PATCH 12/13] OMAP3630: PM: Disable L2 cache while invalidating L2 cache Nishanth Menon
2010-11-19 1:54 ` [PATCH 13/13] OMAP3630: PM: Errata i583: disable coreoff if < ES1.2 Nishanth Menon
2010-11-19 10:07 ` Jean Pihet
2010-11-19 12:14 ` Nishanth Menon
2010-11-19 10:18 ` [PATCH 00/13] OMAP3: OFF mode fixes Jean Pihet
2010-11-19 12:03 ` Nishanth Menon
2010-11-19 21:20 ` Kevin Hilman
2010-11-19 21:37 ` Nishanth Menon
2010-11-20 9:56 ` Santosh Shilimkar
2010-11-22 16:08 ` Kevin Hilman
2010-11-22 19:16 ` Kevin Hilman
2010-11-23 9:02 ` Santosh Shilimkar
2010-11-23 20:35 ` Kevin Hilman
2010-11-24 5:34 ` Santosh Shilimkar
2010-11-24 9:22 ` Santosh Shilimkar
2010-11-24 17:11 ` Jean Pihet
2010-11-24 17:21 ` Nishanth Menon
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