From: Fernando Guzman Lugo <fernando.lugo@ti.com> To: <omar.ramirez@ti.com> Cc: <gregkh@suse.de>, <linux-kernel@vger.kernel.org>, <devel@driverdev.osuosl.org>, <linux-omap@vger.kernel.org>, "Guzman Lugo, Fernando" <fernando.lugo@ti.com>, Felipe Contreras <felipe.contreras@nokia.com> Subject: [PATCHv2] staging: tidspbridge: configure full L1 MMU range Date: Wed, 5 Jan 2011 15:25:33 -0600 [thread overview] Message-ID: <1294262733-9585-1-git-send-email-fernando.lugo@ti.com> (raw) From: Guzman Lugo, Fernando <fernando.lugo@ti.com> IVA MMU can manage up to 4GB of address space through its page tables, given that it's L1 is divided into 1MB sections it requires at least 16KB for its table which represents 4096 entries of 32 bits each. Previously, only 1GB was being handled by setting the page table size to 4KB, any virtual address beyond of the L1 size used, would fall into memory that does not belong to L1 translation tables, leading to unpredictable results. So, set the L1 table size to cover the entire MMU range (4GB) whether is meant to be used or not. Reported-by: Felipe Contreras <felipe.contreras@nokia.com> Signed-off-by: Fernando Guzman Lugo <fernando.lugo@ti.com> Signed-off-by: Felipe Contreras <felipe.contreras@nokia.com> --- drivers/staging/tidspbridge/core/tiomap3430.c | 5 +---- 1 files changed, 1 insertions(+), 4 deletions(-) diff --git a/drivers/staging/tidspbridge/core/tiomap3430.c b/drivers/staging/tidspbridge/core/tiomap3430.c index cacd30e..7608822 100644 --- a/drivers/staging/tidspbridge/core/tiomap3430.c +++ b/drivers/staging/tidspbridge/core/tiomap3430.c @@ -784,10 +784,7 @@ static int bridge_dev_create(struct bridge_dev_context pt_attrs = kzalloc(sizeof(struct pg_table_attrs), GFP_KERNEL); if (pt_attrs != NULL) { - /* Assuming that we use only DSP's memory map - * until 0x4000:0000 , we would need only 1024 - * L1 enties i.e L1 size = 4K */ - pt_attrs->l1_size = 0x1000; + pt_attrs->l1_size = SZ_16K; /* 4096 entries of 32 bits */ align_size = pt_attrs->l1_size; /* Align sizes are expected to be power of 2 */ /* we like to get aligned on L1 table size */ -- 1.7.0.4
WARNING: multiple messages have this Message-ID (diff)
From: Fernando Guzman Lugo <fernando.lugo@ti.com> To: omar.ramirez@ti.com Cc: gregkh@suse.de, linux-kernel@vger.kernel.org, devel@driverdev.osuosl.org, linux-omap@vger.kernel.org, "Guzman Lugo, Fernando" <fernando.lugo@ti.com>, Felipe Contreras <felipe.contreras@nokia.com> Subject: [PATCHv2] staging: tidspbridge: configure full L1 MMU range Date: Wed, 5 Jan 2011 15:25:33 -0600 [thread overview] Message-ID: <1294262733-9585-1-git-send-email-fernando.lugo@ti.com> (raw) From: Guzman Lugo, Fernando <fernando.lugo@ti.com> IVA MMU can manage up to 4GB of address space through its page tables, given that it's L1 is divided into 1MB sections it requires at least 16KB for its table which represents 4096 entries of 32 bits each. Previously, only 1GB was being handled by setting the page table size to 4KB, any virtual address beyond of the L1 size used, would fall into memory that does not belong to L1 translation tables, leading to unpredictable results. So, set the L1 table size to cover the entire MMU range (4GB) whether is meant to be used or not. Reported-by: Felipe Contreras <felipe.contreras@nokia.com> Signed-off-by: Fernando Guzman Lugo <fernando.lugo@ti.com> Signed-off-by: Felipe Contreras <felipe.contreras@nokia.com> --- drivers/staging/tidspbridge/core/tiomap3430.c | 5 +---- 1 files changed, 1 insertions(+), 4 deletions(-) diff --git a/drivers/staging/tidspbridge/core/tiomap3430.c b/drivers/staging/tidspbridge/core/tiomap3430.c index cacd30e..7608822 100644 --- a/drivers/staging/tidspbridge/core/tiomap3430.c +++ b/drivers/staging/tidspbridge/core/tiomap3430.c @@ -784,10 +784,7 @@ static int bridge_dev_create(struct bridge_dev_context pt_attrs = kzalloc(sizeof(struct pg_table_attrs), GFP_KERNEL); if (pt_attrs != NULL) { - /* Assuming that we use only DSP's memory map - * until 0x4000:0000 , we would need only 1024 - * L1 enties i.e L1 size = 4K */ - pt_attrs->l1_size = 0x1000; + pt_attrs->l1_size = SZ_16K; /* 4096 entries of 32 bits */ align_size = pt_attrs->l1_size; /* Align sizes are expected to be power of 2 */ /* we like to get aligned on L1 table size */ -- 1.7.0.4
next reply other threads:[~2011-01-05 21:25 UTC|newest] Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top 2011-01-05 21:25 Fernando Guzman Lugo [this message] 2011-01-05 21:25 ` [PATCHv2] staging: tidspbridge: configure full L1 MMU range Fernando Guzman Lugo 2011-01-14 1:39 ` Ramirez Luna, Omar
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=1294262733-9585-1-git-send-email-fernando.lugo@ti.com \ --to=fernando.lugo@ti.com \ --cc=devel@driverdev.osuosl.org \ --cc=felipe.contreras@nokia.com \ --cc=gregkh@suse.de \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-omap@vger.kernel.org \ --cc=omar.ramirez@ti.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.