[PATCH] drm/i915: Use TILECTL on SNB to detect swizzle mode

[Chris Wilson <chris@chris-wilson.co.uk>]

We're meant to set this bit based on DRAM configuration...

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---

Jesse, does this suggest anything unusual for TILECLT on your weird system?
Also do you know which DRAM config bits it is referring to?
-Chris

---
 drivers/gpu/drm/i915/i915_gem_tiling.c |   29 ++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/i915_reg.h        |    3 +++
 drivers/gpu/drm/i915/intel_display.c   |    8 ++++++--
 3 files changed, 37 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 22a32b9..bc19fb2 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -92,7 +92,34 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
 	uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
 	uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
 
-	if (IS_GEN5(dev) || IS_GEN6(dev)) {
+	if (IS_GEN6(dev)) {
+		/* TILECTL 0x10100 (uncore):
+		 * [1:0] Address Swizzling for Tiled-Surfaces (SWZCTL):
+		 * This register location is updated via GFX Driver prior to
+		 * enabling DRAM accesses.  The Driver needs to obtain the need
+		 * for memory address swizzling via DRAM configuration registers
+		 * and set the following bits.
+		 *
+		 * 00b - No Address Swizzling
+		 * 01b - Address bit [6] needs to be swizzled for tiled surfaces
+		 * 10b - Reserved
+		 * 11b - Reserved
+		 */
+		printk(KERN_ERR "tilectl = %x\n", I915_READ(GEN6_TILECTL));
+		switch (I915_READ(GEN6_TILECTL) & 0x3) {
+		default:
+			DRM_ERROR("unknown swizzle mode for tiled surfaces: %x\n",
+				  I915_READ(GEN6_TILECTL));
+		case 0:
+			swizzle_x = I915_BIT_6_SWIZZLE_NONE;
+			swizzle_y = I915_BIT_6_SWIZZLE_NONE;
+			break;
+		case 1:
+			swizzle_x = I915_BIT_6_SWIZZLE_9_10;
+			swizzle_y = I915_BIT_6_SWIZZLE_9;
+			break;
+		}
+	} else if (IS_GEN5(dev)) {
 		/* On Ironlake whatever DRAM config, GPU always do
 		 * same swizzling setup.
 		 */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 15d94c6..49bae1a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2781,8 +2781,11 @@
 
 #define DISP_ARB_CTL	0x45000
 #define  DISP_TILE_SURFACE_SWIZZLING	(1<<13)
+#define  DISP_TILE_MASK			(3<<13)
 #define  DISP_FBC_WM_DIS		(1<<15)
 
+#define GEN6_TILECTL 0x101000
+
 /* PCH */
 
 /* south display engine interrupt */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3b00653..94b6030 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4457,10 +4457,14 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
 
 	intel_wait_for_vblank(dev, pipe);
 
+	/* enable address swizzle for tiling scanout */
 	if (IS_GEN5(dev)) {
-		/* enable address swizzle for tiling buffer */
-		temp = I915_READ(DISP_ARB_CTL);
+		temp = I915_READ(DISP_ARB_CTL) & ~DISP_TILE_MASK;
 		I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
+	} else if (IS_GEN6 (dev)) {
+		temp = I915_READ(DISP_ARB_CTL) & ~DISP_TILE_MASK;
+		temp |= (I915_READ(GEN6_TILECTL) & 0x3) << 13;
+		I915_WRITE(DISP_ARB_CTL, temp);
 	}
 
 	I915_WRITE(DSPCNTR(plane), dspcntr);
-- 
1.7.2.3