All of lore.kernel.org
 help / color / mirror / Atom feed
From: Zhenyu Wang <zhenyuw@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 4/4] drm/i915: move sandybridge RC6 enable in resume after ring initialization
Date: Wed, 23 Mar 2011 10:21:09 +0800	[thread overview]
Message-ID: <1300846869-28245-5-git-send-email-zhenyuw@linux.intel.com> (raw)
In-Reply-To: <1300846869-28245-1-git-send-email-zhenyuw@linux.intel.com>

Move RC6 enable after we reset rings for all regines, if e.g render ring
is disabled when RC6 enable on Sandybridge, hw won't save render context
image if any chance when enter RC6. Also match the order like we do in
driver load.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c     |    3 +++
 drivers/gpu/drm/i915/i915_suspend.c |    3 ---
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 22ec066..e675ba9 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -378,6 +378,9 @@ static int i915_drm_thaw(struct drm_device *dev)
 
 		if (IS_IRONLAKE_M(dev))
 			ironlake_enable_rc6(dev);
+
+		if (IS_GEN6(dev))
+			gen6_enable_rps(dev_priv);
 	}
 
 	intel_opregion_init(dev);
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index bce24d8..08c1d04 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -875,9 +875,6 @@ int i915_restore_state(struct drm_device *dev)
 		intel_init_emon(dev);
 	}
 
-	if (IS_GEN6(dev))
-		gen6_enable_rps(dev_priv);
-
 	/* Cache mode state */
 	I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
 
-- 
1.7.4.1

  parent reply	other threads:[~2011-03-23  2:21 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-03-23  2:21 [PATCH 0/4 rev2] Sandybridge suspend/resume fixes Zhenyu Wang
2011-03-23  2:21 ` [PATCH 1/4] drm/i915: clock gating fix for gen5 and gen6 Zhenyu Wang
2011-03-23  2:21 ` [PATCH 2/4] drm/i915: save/restore DSPARB only for chips before gen4 but not for G33 Zhenyu Wang
2011-03-23  3:03   ` Keith Packard
2011-03-23  4:20     ` Zhenyu Wang
2011-03-23  2:21 ` [PATCH 3/4] drm/i915: save/restore MI_ARB_STATE only before gen6 Zhenyu Wang
2011-03-23  2:21 ` Zhenyu Wang [this message]
2011-03-23  6:22 ` [PATCH 0/4 rev2] Sandybridge suspend/resume fixes Fu Michael

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1300846869-28245-5-git-send-email-zhenyuw@linux.intel.com \
    --to=zhenyuw@linux.intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.