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From: Eric Anholt <eric@anholt.net>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 8/9] drm/i915: Clean up leftover DPLL and LVDS register choice from pch split.
Date: Wed, 30 Mar 2011 13:01:09 -0700	[thread overview]
Message-ID: <1301515270-3768-9-git-send-email-eric@anholt.net> (raw)
In-Reply-To: <1301515270-3768-1-git-send-email-eric@anholt.net>

We used to have these from the product of (pch, non-pch) * (pipe a,
pipe b).  Now we can just use the nice per-pipe reg macros in the
split out crtc_mode_sets.

Signed-off-by: Eric Anholt <eric@anholt.net>
---
 drivers/gpu/drm/i915/intel_display.c |   57 +++++++++++++---------------------
 1 files changed, 22 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 41d82b5..8de3473 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4524,7 +4524,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
 	int plane = intel_crtc->plane;
-	u32 fp_reg, dpll_reg;
 	int refclk, num_connectors = 0;
 	intel_clock_t clock, reduced_clock;
 	u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
@@ -4534,7 +4533,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 	struct intel_encoder *encoder;
 	const intel_limit_t *limit;
 	int ret;
-	u32 reg, temp;
+	u32 temp;
 	u32 lvds_sync = 0;
 
 	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
@@ -4740,13 +4739,10 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 	DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
 	drm_mode_debug_printmodeline(mode);
 
-	fp_reg = FP0(pipe);
-	dpll_reg = DPLL(pipe);
+	I915_WRITE(FP0(pipe), fp);
+	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
 
-	I915_WRITE(fp_reg, fp);
-	I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
-
-	POSTING_READ(dpll_reg);
+	POSTING_READ(DPLL(pipe));
 	udelay(150);
 
 	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
@@ -4754,9 +4750,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 	 * things on.
 	 */
 	if (is_lvds) {
-		reg = LVDS;
-
-		temp = I915_READ(reg);
+		temp = I915_READ(LVDS);
 		temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
 		if (pipe == 1) {
 			temp |= LVDS_PIPEB_SELECT;
@@ -4800,17 +4794,17 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 			temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
 			temp |= lvds_sync;
 		}
-		I915_WRITE(reg, temp);
+		I915_WRITE(LVDS, temp);
 	}
 
 	if (is_dp) {
 		intel_dp_set_m_n(crtc, mode, adjusted_mode);
 	}
 
-	I915_WRITE(dpll_reg, dpll);
+	I915_WRITE(DPLL(pipe), dpll);
 
 	/* Wait for the clocks to stabilize. */
-	POSTING_READ(dpll_reg);
+	POSTING_READ(DPLL(pipe));
 	udelay(150);
 
 	if (INTEL_INFO(dev)->gen >= 4) {
@@ -4829,19 +4823,19 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 		 *
 		 * So write it again.
 		 */
-		I915_WRITE(dpll_reg, dpll);
+		I915_WRITE(DPLL(pipe), dpll);
 	}
 
 	intel_crtc->lowfreq_avail = false;
 	if (is_lvds && has_reduced_clock && i915_powersave) {
-		I915_WRITE(fp_reg + 4, fp2);
+		I915_WRITE(FP1(pipe), fp2);
 		intel_crtc->lowfreq_avail = true;
 		if (HAS_PIPE_CXSR(dev)) {
 			DRM_DEBUG_KMS("enabling CxSR downclocking\n");
 			pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
 		}
 	} else {
-		I915_WRITE(fp_reg + 4, fp);
+		I915_WRITE(FP1(pipe), fp);
 		if (HAS_PIPE_CXSR(dev)) {
 			DRM_DEBUG_KMS("disabling CxSR downclocking\n");
 			pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
@@ -4918,7 +4912,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
 	int plane = intel_crtc->plane;
-	u32 fp_reg, dpll_reg;
 	int refclk, num_connectors = 0;
 	intel_clock_t clock, reduced_clock;
 	u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
@@ -4930,7 +4923,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 	const intel_limit_t *limit;
 	int ret;
 	struct fdi_m_n m_n = {0};
-	u32 reg, temp;
+	u32 temp;
 	u32 lvds_sync = 0;
 	int target_clock, pixel_multiplier, lane, link_bw, bpp, factor;
 
@@ -5236,16 +5229,12 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 	DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
 	drm_mode_debug_printmodeline(mode);
 
-	/* assign to Ironlake registers */
-	fp_reg = PCH_FP0(pipe);
-	dpll_reg = PCH_DPLL(pipe);
-
 	/* PCH eDP needs FDI, but CPU eDP does not */
 	if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
-		I915_WRITE(fp_reg, fp);
-		I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
+		I915_WRITE(PCH_FP0(pipe), fp);
+		I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
 
-		POSTING_READ(dpll_reg);
+		POSTING_READ(PCH_DPLL(pipe));
 		udelay(150);
 	}
 
@@ -5277,9 +5266,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 	 * things on.
 	 */
 	if (is_lvds) {
-		reg = PCH_LVDS;
-
-		temp = I915_READ(reg);
+		temp = I915_READ(PCH_LVDS);
 		temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
 		if (pipe == 1) {
 			if (HAS_PCH_CPT(dev))
@@ -5322,7 +5309,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 			temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
 			temp |= lvds_sync;
 		}
-		I915_WRITE(reg, temp);
+		I915_WRITE(PCH_LVDS, temp);
 	}
 
 	/* set the dithering flag and clear for anything other than a panel. */
@@ -5345,10 +5332,10 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 
 	if (!has_edp_encoder ||
 	    intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
-		I915_WRITE(dpll_reg, dpll);
+		I915_WRITE(PCH_DPLL(pipe), dpll);
 
 		/* Wait for the clocks to stabilize. */
-		POSTING_READ(dpll_reg);
+		POSTING_READ(PCH_DPLL(pipe));
 		udelay(150);
 
 		/* The pixel multiplier can only be updated once the
@@ -5356,19 +5343,19 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 		 *
 		 * So write it again.
 		 */
-		I915_WRITE(dpll_reg, dpll);
+		I915_WRITE(PCH_DPLL(pipe), dpll);
 	}
 
 	intel_crtc->lowfreq_avail = false;
 	if (is_lvds && has_reduced_clock && i915_powersave) {
-		I915_WRITE(fp_reg + 4, fp2);
+		I915_WRITE(PCH_FP1(pipe), fp2);
 		intel_crtc->lowfreq_avail = true;
 		if (HAS_PIPE_CXSR(dev)) {
 			DRM_DEBUG_KMS("enabling CxSR downclocking\n");
 			pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
 		}
 	} else {
-		I915_WRITE(fp_reg + 4, fp);
+		I915_WRITE(PCH_FP1(pipe), fp);
 		if (HAS_PIPE_CXSR(dev)) {
 			DRM_DEBUG_KMS("disabling CxSR downclocking\n");
 			pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
-- 
1.7.4.1

  parent reply	other threads:[~2011-03-30 20:01 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-03-30 20:01 Splitting HAS_PCH_SPLIT code in intel_crtc_mode_set() Eric Anholt
2011-03-30 20:01 ` [PATCH 1/9] drm/i915: Split the crtc_mode_set function along HAS_PCH_SPLIT() lines Eric Anholt
2011-03-30 20:12   ` Jesse Barnes
2011-03-30 20:01 ` [PATCH 2/9] drm/i915: Move the vblank pre/post modeset to the common crtc_mode_set Eric Anholt
2011-03-30 20:13   ` Jesse Barnes
2011-03-30 20:01 ` [PATCH 3/9] drm/i915: Remove the PCH paths from the pre-Ironlake crtc_mode_set() Eric Anholt
2011-03-30 20:15   ` Jesse Barnes
2011-03-30 20:01 ` [PATCH 4/9] drm/i915: Drop the eDP paths from the pre-Ironlake crtc_mode_set Eric Anholt
2011-03-30 20:34   ` Jesse Barnes
2011-03-30 20:01 ` [PATCH 5/9] drm/i915: Drop the remaining bit of Ironlake code from i9xx_crtc_mode_set() Eric Anholt
2011-03-30 20:34   ` Jesse Barnes
2011-03-30 20:01 ` [PATCH 6/9] drm/i915: Drop non-HAS_PCH_SPLIT() code from ironlake_crtc_mode_set() Eric Anholt
2011-03-31 11:43   ` Chris Wilson
2011-03-31 16:09   ` Jesse Barnes
2011-03-30 20:01 ` [PATCH 7/9] drm/i915: Drop remaining pre-Ironlake " Eric Anholt
2011-03-31 16:09   ` Jesse Barnes
2011-03-30 20:01 ` Eric Anholt [this message]
2011-03-31 16:12   ` [PATCH 8/9] drm/i915: Clean up leftover DPLL and LVDS register choice from pch split Jesse Barnes
2011-03-30 20:01 ` [PATCH 9/9] drm/i915: Fold the DPLL limit defines into the structs that use them Eric Anholt
2011-03-31 16:12   ` Jesse Barnes
2011-03-31  7:34 ` Splitting HAS_PCH_SPLIT code in intel_crtc_mode_set() Chris Wilson

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