[PATCH 1/2] i965: Stop caching the combined depth/stencil region in brw_context.c.

[Eric Anholt <eric@anholt.net>]

This was going to get in the way of separate depth/stencil (which
wants to know about both, and whether they are the same rb), and also
wasn't a sufficient flag for the fix in the following commit.
---
 src/mesa/drivers/dri/i965/brw_context.h      |   24 -----------------
 src/mesa/drivers/dri/i965/brw_misc_state.c   |   36 ++++++++++++++++++--------
 src/mesa/drivers/dri/i965/brw_state_upload.c |    1 -
 src/mesa/drivers/dri/i965/brw_vtbl.c         |    9 ------
 src/mesa/drivers/dri/i965/brw_wm_state.c     |    6 ++--
 5 files changed, 28 insertions(+), 48 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 26cd820..f351bcd 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -139,8 +139,6 @@ struct brw_context;
  * by any 3D rendering.
  */
 #define BRW_NEW_BATCH			0x10000
-/** \see brw.state.depth_region */
-#define BRW_NEW_DEPTH_BUFFER		0x20000
 #define BRW_NEW_NR_WM_SURFACES		0x40000
 #define BRW_NEW_NR_VS_SURFACES		0x80000
 #define BRW_NEW_INDEX_BUFFER		0x100000
@@ -462,28 +460,6 @@ struct brw_context
 
    struct {
       struct brw_state_flags dirty;
-
-      /**
-       * \name Cached region pointers
-       *
-       * When the draw buffer is updated, often the depth buffer is not
-       * changed. Caching the pointer to the buffer's region allows us to
-       * detect when the buffer has in fact changed, and allows us to avoid
-       * updating the buffer's GPU state when it has not.
-       *
-       * The original of each cached pointer is an instance of
-       * \c intel_renderbuffer.region.
-       *
-       * \see brw_set_draw_region()
-       *
-       * \{
-       */
-
-      /** \see struct brw_tracked_state brw_depthbuffer */
-      struct intel_region *depth_region;
-
-      /** \} */
-
       /**
        * List of buffers accumulated in brw_validate_state to receive
        * drm_intel_bo_check_aperture treatment before exec, so we can
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 7119786..e8c8b81 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -32,6 +32,7 @@
 
 
 #include "intel_batchbuffer.h"
+#include "intel_fbo.h"
 #include "intel_regions.h"
 
 #include "brw_context.h"
@@ -187,18 +188,33 @@ const struct brw_tracked_state brw_psp_urb_cbs = {
 
 static void prepare_depthbuffer(struct brw_context *brw)
 {
-   struct intel_region *region = brw->state.depth_region;
-
-   if (region != NULL)
-      brw_add_validated_bo(brw, region->buffer);
+   struct intel_context *intel = &brw->intel;
+   struct gl_context *ctx = &intel->ctx;
+   struct gl_framebuffer *fb = ctx->DrawBuffer;
+   struct intel_renderbuffer *drb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
+   struct intel_renderbuffer *srb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
+
+   if (drb)
+      brw_add_validated_bo(brw, drb->region->buffer);
+   if (srb)
+      brw_add_validated_bo(brw, srb->region->buffer);
 }
 
 static void emit_depthbuffer(struct brw_context *brw)
 {
    struct intel_context *intel = &brw->intel;
-   struct intel_region *region = brw->state.depth_region;
+   struct gl_context *ctx = &intel->ctx;
+   struct gl_framebuffer *fb = ctx->DrawBuffer;
+   /* _NEW_BUFFERS */
+   struct intel_renderbuffer *irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
    unsigned int len;
 
+   /* If we're combined depth stencil but no depth is attached, look
+    * up stencil.
+    */
+   if (!irb)
+      irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
+
    if (intel->gen >= 6)
       len = 7;
    else if (intel->is_g4x || intel->gen == 5)
@@ -206,7 +222,7 @@ static void emit_depthbuffer(struct brw_context *brw)
    else
       len = 5;
 
-   if (region == NULL) {
+   if (!irb) {
       BEGIN_BATCH(len);
       OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
       OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |
@@ -223,6 +239,7 @@ static void emit_depthbuffer(struct brw_context *brw)
 
       ADVANCE_BATCH();
    } else {
+      struct intel_region *region = irb->region;
       unsigned int format;
 
       switch (region->cpp) {
@@ -276,13 +293,10 @@ static void emit_depthbuffer(struct brw_context *brw)
    }
 }
 
-/**
- * \see brw_context.state.depth_region
- */
 const struct brw_tracked_state brw_depthbuffer = {
    .dirty = {
-      .mesa = 0,
-      .brw = BRW_NEW_DEPTH_BUFFER | BRW_NEW_BATCH,
+      .mesa = _NEW_BUFFERS,
+      .brw = BRW_NEW_BATCH,
       .cache = 0,
    },
    .prepare = prepare_depthbuffer,
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 008aceb..0bd36a0 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -304,7 +304,6 @@ static struct dirty_bit_map brw_bits[] = {
    DEFINE_BIT(BRW_NEW_INDEX_BUFFER),
    DEFINE_BIT(BRW_NEW_VERTICES),
    DEFINE_BIT(BRW_NEW_BATCH),
-   DEFINE_BIT(BRW_NEW_DEPTH_BUFFER),
    DEFINE_BIT(BRW_NEW_NR_WM_SURFACES),
    DEFINE_BIT(BRW_NEW_NR_VS_SURFACES),
    DEFINE_BIT(BRW_NEW_VS_CONSTBUF),
diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c b/src/mesa/drivers/dri/i965/brw_vtbl.c
index f2c417d..5515038 100644
--- a/src/mesa/drivers/dri/i965/brw_vtbl.c
+++ b/src/mesa/drivers/dri/i965/brw_vtbl.c
@@ -72,8 +72,6 @@ static void brw_destroy_context( struct intel_context *intel )
       free(brw->wm.compile_data);
    }
 
-   intel_region_release(&brw->state.depth_region);
-
    dri_bo_release(&brw->curbe.curbe_bo);
    dri_bo_release(&brw->vs.prog_bo);
    dri_bo_release(&brw->vs.const_bo);
@@ -97,13 +95,6 @@ static void brw_set_draw_region( struct intel_context *intel,
                                  struct intel_region *depth_region,
                                  GLuint num_color_regions)
 {
-   struct brw_context *brw = brw_context(&intel->ctx);
-
-   if (brw->state.depth_region != depth_region) {
-      brw->state.dirty.brw |= BRW_NEW_DEPTH_BUFFER;
-      intel_region_release(&brw->state.depth_region);
-      intel_region_reference(&brw->state.depth_region, depth_region);
-   }
 }
 
 
diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index a91ae51..a356711 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -31,6 +31,7 @@
                    
 
 
+#include "intel_fbo.h"
 #include "brw_context.h"
 #include "brw_state.h"
 #include "brw_defines.h"
@@ -144,11 +145,11 @@ brw_prepare_wm_unit(struct brw_context *brw)
 				 (1 << FRAG_ATTRIB_WPOS)) != 0;
    wm->wm5.program_computes_depth = (fp->Base.OutputsWritten &
 				     BITFIELD64_BIT(FRAG_RESULT_DEPTH)) != 0;
-   /* BRW_NEW_DEPTH_BUFFER
+   /* _NEW_BUFFERS
     * Override for NULL depthbuffer case, required by the Pixel Shader Computed
     * Depth field.
     */
-   if (brw->state.depth_region == NULL)
+   if (!intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH))
       wm->wm5.program_computes_depth = 0;
 
    /* _NEW_COLOR */
@@ -266,7 +267,6 @@ const struct brw_tracked_state brw_wm_unit = {
       .brw = (BRW_NEW_BATCH |
 	      BRW_NEW_FRAGMENT_PROGRAM |
 	      BRW_NEW_CURBE_OFFSETS |
-	      BRW_NEW_DEPTH_BUFFER |
 	      BRW_NEW_NR_WM_SURFACES),
 
       .cache = (CACHE_NEW_WM_PROG |
-- 
1.7.5.1