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From: Chad Versace <chad@chad-versace.us>
To: intel-gfx@lists.freedesktop.org, mesa-dev@lists.freedesktop.org
Cc: Chad Versace <chad@chad-versace.us>,
	Ian Romancik <ian.d.romanick@intel.com>
Subject: [PATCH] dri: Do not tile stencil buffer
Date: Mon, 18 Jul 2011 17:08:34 -0700	[thread overview]
Message-ID: <1311034115-4191-2-git-send-email-chad@chad-versace.us> (raw)
In-Reply-To: <1311034115-4191-1-git-send-email-chad@chad-versace.us>

Until now, the stencil buffer was allocated as a Y tiled buffer, because
in several locations the PRM states that it is. However, it is actually
W tiled. From the PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section
4.5.2.1 W-Major Format:
    W-Major Tile Format is used for separate stencil.

The GTT is incapable of W fencing, so we allocate the stencil buffer with
I915_TILING_NONE and decode the tile's layout in software.

This commit mutually depends on the mesa commit:
    intel: Fix stencil buffer to be W tiled
    Author: Chad Versace <chad@chad-versace.us>
    Date:   Mon Jul 18 00:37:45 2011 -0700

CC: Eric Anholt <eric@anholt.net>
CC: Kenneth Graunke <kenneth@whitecape.org>
CC: Ian Romancik <ian.d.romanick@intel.com>
Signed-off-by: Chad Versace <chad@chad-versace.us>
---
 src/intel_dri.c |   16 ++++++++++++----
 1 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/src/intel_dri.c b/src/intel_dri.c
index 1269422..90abe5f 100644
--- a/src/intel_dri.c
+++ b/src/intel_dri.c
@@ -335,7 +335,6 @@ I830DRI2CreateBuffer(DrawablePtr drawable, unsigned int attachment,
 			switch (attachment) {
 			case DRI2BufferDepth:
 			case DRI2BufferDepthStencil:
-			case DRI2BufferStencil:
 			case DRI2BufferHiz:
 				if (SUPPORTS_YTILING(intel)) {
 					hint |= INTEL_CREATE_PIXMAP_TILING_Y;
@@ -350,6 +349,14 @@ I830DRI2CreateBuffer(DrawablePtr drawable, unsigned int attachment,
 			case DRI2BufferFrontRight:
 				hint |= INTEL_CREATE_PIXMAP_TILING_X;
 				break;
+			case DRI2BufferStencil:
+				/*
+				 * The stencil buffer is W tiled. However, we
+				 * request from the kernel a non-tiled buffer
+				 * because the GTT is incapable of W fencing.
+				 */
+				hint |= INTEL_CREATE_PIXMAP_TILING_NONE;
+				break;
 			default:
 				free(privates);
 				free(buffer);
@@ -367,11 +374,12 @@ I830DRI2CreateBuffer(DrawablePtr drawable, unsigned int attachment,
 		 * To accomplish this, we resort to the nasty hack of doubling
 		 * the drm region's cpp and halving its height.
 		 *
-		 * If we neglect to double the pitch, then
-		 * drm_intel_gem_bo_map_gtt() maps the memory incorrectly.
+		 * If we neglect to double the pitch, then render corruption
+		 * occurs.
 		 */
 		if (attachment == DRI2BufferStencil) {
-			pixmap_height /= 2;
+			pixmap_width = ALIGN(pixmap_width, 64);
+			pixmap_height = ALIGN((pixmap_height + 1) / 2, 64);
 			pixmap_cpp *= 2;
 		}
 
-- 
1.7.6

  reply	other threads:[~2011-07-19  0:08 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-07-19  0:08 [PATCH v2] intel: Fix stencil buffer to be W tiled Chad Versace
2011-07-19  0:08 ` Chad Versace [this message]
2011-07-19  0:18   ` [PATCH] dri: Do not tile stencil buffer Kenneth Graunke
2011-07-19  0:08 ` [PATCH] intel: Fix stencil buffer to be W tiled Chad Versace
  -- strict thread matches above, loose matches on Subject: below --
2011-07-18  7:55 Chad Versace
2011-07-18  7:55 ` [PATCH] dri: Do not tile stencil buffer Chad Versace
2011-07-18  8:15   ` Paul Menzel

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