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From: Jesse Barnes <jbarnes@virtuousgeek.org>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 1/2] drm/i915: apply phase pointer override on SNB+ too
Date: Thu, 28 Jul 2011 12:55:13 -0700	[thread overview]
Message-ID: <1311882914-11676-1-git-send-email-jbarnes@virtuousgeek.org> (raw)

These bits moved around on SNB and above.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_reg.h      |    7 +++++++
 drivers/gpu/drm/i915/intel_display.c |   34 ++++++++++++++++++++++++++++++++++
 2 files changed, 41 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7377ae4..ae28549 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3081,6 +3081,13 @@
 #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
 #define   TRANS_AUTOTRAIN_GEN_STALL_DIS	(1<<31)
 
+#define SOUTH_CHICKEN1		0xc2000
+#define  FDIA_PHASE_SYNC_OVR	(1<<19)
+#define  FDIA_PHASE_SYNC_EN	(1<<18)
+#define  FDIB_PHASE_SYNC_OVR	(1<<17)
+#define  FDIB_PHASE_SYNC_EN	(1<<16)
+#define  FDIC_PHASE_SYNC_OVR	(1<<15)
+#define  FDIC_PHASE_SYNC_EN	(1<<14)
 #define SOUTH_CHICKEN2		0xc2004
 #define  DPLS_EDP_PPS_FIX_DIS	(1<<0)
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 73bf235..2a367de 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2295,6 +2295,23 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
 		I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
 		I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
 			   FDI_RX_PHASE_SYNC_POINTER_EN);
+	} else if (HAS_PCH_CPT(dev)) {
+		u32 flags;
+		switch (pipe) {
+		case 0:
+			flags = FDIA_PHASE_SYNC_OVR | FDIA_PHASE_SYNC_EN;
+			break;
+		case 2:
+			flags = FDIA_PHASE_SYNC_OVR | FDIA_PHASE_SYNC_EN;
+			break;
+		case 3:
+			flags = FDIA_PHASE_SYNC_OVR | FDIA_PHASE_SYNC_EN;
+			break;
+		default:
+			break;
+		}
+		I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
+		I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
 	}
 
 	reg = FDI_RX_IIR(pipe);
@@ -2652,6 +2669,23 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc)
 		I915_WRITE(FDI_RX_CHICKEN(pipe),
 			   I915_READ(FDI_RX_CHICKEN(pipe) &
 				     ~FDI_RX_PHASE_SYNC_POINTER_EN));
+	} else if (HAS_PCH_CPT(dev)) {
+		u32 flags;
+		switch (pipe) {
+		case 0:
+			flags = FDIA_PHASE_SYNC_OVR;
+			break;
+		case 2:
+			flags = FDIA_PHASE_SYNC_OVR;
+			break;
+		case 3:
+			flags = FDIA_PHASE_SYNC_OVR;
+			break;
+		default:
+			break;
+		}
+		I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
+		I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
 	}
 
 	/* still set train pattern 1 */
-- 
1.7.4.1

             reply	other threads:[~2011-07-28 19:55 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-07-28 19:55 Jesse Barnes [this message]
2011-07-28 19:55 ` [PATCH 2/2] drm/i915: don't use uninitialized EDID bpc values when picking pipe bpp Jesse Barnes

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