All of lore.kernel.org
 help / color / mirror / Atom feed
From: Dave Martin <dave.martin@linaro.org>
To: linux-arm-kernel@lists.infradead.org
Cc: linux-tegra@vger.kernel.org, Colin Cross <ccross@android.com>,
	patches@linaro.org
Subject: [PATCH] ARM: tegra: Remove redundant change to the CPSR in headsmp.S
Date: Wed,  7 Sep 2011 17:00:53 +0100	[thread overview]
Message-ID: <1315411253-17559-1-git-send-email-dave.martin@linaro.org> (raw)

At secondary_startup, the MSR CPSR_cxsf, #0xd3 is not compatible
with Thumb-2 and also unmasks asynchronous aborts (CPSR.A bit
forced to zero -- this is probably unintentional).

Any remotely sane bootloader should be putting each secondary CPU
in the appropriate state _before_ entering the kernel anyway.
Otherwise, disabling interrupts on entry to the kernel isn't going
to fix it.

Therefore this patch just removes the MSR instruction.

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---

I make assumptions about the bootloader in this patch.  If someone with
Tegra knowledge can please comment and/or test, that would be much
appreciated, thanks.

 arch/arm/mach-tegra/headsmp.S |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index b5349b2..6ec4790 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -48,7 +48,6 @@ ENTRY(v7_invalidate_l1)
 ENDPROC(v7_invalidate_l1)
 
 ENTRY(tegra_secondary_startup)
-	msr	cpsr_fsxc, #0xd3
         bl      v7_invalidate_l1
 	mrc	p15, 0, r0, c0, c0, 5
         and	r0, r0, #15
-- 
1.7.4.1

WARNING: multiple messages have this Message-ID (diff)
From: dave.martin@linaro.org (Dave Martin)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] ARM: tegra: Remove redundant change to the CPSR in headsmp.S
Date: Wed,  7 Sep 2011 17:00:53 +0100	[thread overview]
Message-ID: <1315411253-17559-1-git-send-email-dave.martin@linaro.org> (raw)

At secondary_startup, the MSR CPSR_cxsf, #0xd3 is not compatible
with Thumb-2 and also unmasks asynchronous aborts (CPSR.A bit
forced to zero -- this is probably unintentional).

Any remotely sane bootloader should be putting each secondary CPU
in the appropriate state _before_ entering the kernel anyway.
Otherwise, disabling interrupts on entry to the kernel isn't going
to fix it.

Therefore this patch just removes the MSR instruction.

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---

I make assumptions about the bootloader in this patch.  If someone with
Tegra knowledge can please comment and/or test, that would be much
appreciated, thanks.

 arch/arm/mach-tegra/headsmp.S |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index b5349b2..6ec4790 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -48,7 +48,6 @@ ENTRY(v7_invalidate_l1)
 ENDPROC(v7_invalidate_l1)
 
 ENTRY(tegra_secondary_startup)
-	msr	cpsr_fsxc, #0xd3
         bl      v7_invalidate_l1
 	mrc	p15, 0, r0, c0, c0, 5
         and	r0, r0, #15
-- 
1.7.4.1

             reply	other threads:[~2011-09-07 16:00 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-09-07 16:00 Dave Martin [this message]
2011-09-07 16:00 ` [PATCH] ARM: tegra: Remove redundant change to the CPSR in headsmp.S Dave Martin
     [not found] ` <1315411253-17559-1-git-send-email-dave.martin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2011-09-12 16:52   ` Dave Martin
2011-09-12 16:52     ` Dave Martin
     [not found]     ` <20110912165222.GE2020-5wv7dgnIgG8@public.gmane.org>
2011-09-14  1:46       ` Colin Cross
2011-09-14  1:46         ` Colin Cross
2011-09-14  9:15         ` Dave Martin
2011-09-14  9:15           ` Dave Martin
     [not found]           ` <20110914091531.GA2104-5wv7dgnIgG8@public.gmane.org>
2011-09-21 16:14             ` Colin Cross
2011-09-21 16:14               ` Colin Cross

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1315411253-17559-1-git-send-email-dave.martin@linaro.org \
    --to=dave.martin@linaro.org \
    --cc=ccross@android.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-tegra@vger.kernel.org \
    --cc=patches@linaro.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.