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From: "Marek Olšák" <maraeo@gmail.com>
To: dri-devel@lists.freedesktop.org
Subject: [PATCH 2/2] radeon: optimize allocation for depth w/o stencil and stencil w/o depth on EG
Date: Sun, 29 Jul 2012 16:02:02 +0200	[thread overview]
Message-ID: <1343570522-4080-2-git-send-email-maraeo@gmail.com> (raw)
In-Reply-To: <1343570522-4080-1-git-send-email-maraeo@gmail.com>

If we don't need stencil, don't allocate it.
If we need only stencil (like PIPE_FORMAT_S8_UINT), don't allocate depth.
---
 radeon/radeon_surface.c |   19 +++++--------------
 1 file changed, 5 insertions(+), 14 deletions(-)

diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index 5800c33..fcfefdc 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -604,7 +604,10 @@ static int eg_surface_init_1d(struct radeon_surface_manager *surf_man,
         }
     }
 
-    if (surf->flags & RADEON_SURF_SBUFFER) {
+    /* The depth and stencil buffers are in separate resources on evergreen.
+     * We allocate them in one buffer next to each other to simplify
+     * communication between the DDX and the Mesa driver. */
+    if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) {
         surf->stencil_offset = ALIGN(surf->bo_size, surf->bo_alignment);
         surf->bo_size = surf->stencil_offset + surf->bo_size / 4;
     }
@@ -752,14 +755,7 @@ static int eg_surface_init(struct radeon_surface_manager *surf_man,
     /* tiling mode */
     mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
 
-    /* for some reason eg need to have room for stencil right after depth */
-    if (surf->flags & RADEON_SURF_ZBUFFER) {
-        surf->flags |= RADEON_SURF_SBUFFER;
-    }
-    if (surf->flags & RADEON_SURF_SBUFFER) {
-        surf->flags |= RADEON_SURF_ZBUFFER;
-    }
-    if (surf->flags & RADEON_SURF_ZBUFFER) {
+    if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) {
         /* zbuffer only support 1D or 2D tiled surface */
         switch (mode) {
         case RADEON_SURF_MODE_1D:
@@ -828,11 +824,6 @@ static int eg_surface_best(struct radeon_surface_manager *surf_man,
     /* tiling mode */
     mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
 
-    /* for some reason eg need to have room for stencil right after depth */
-    if (surf->flags & RADEON_SURF_ZBUFFER) {
-        surf->flags |= RADEON_SURF_SBUFFER;
-    }
-
     /* set some default value to avoid sanity check choking on them */
     surf->tile_split = 1024;
     surf->bankw = 1;
-- 
1.7.9.5

  reply	other threads:[~2012-07-29 14:02 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-07-29 14:02 [PATCH 1/2] radeon: simplify ZS buffer checking on r600 Marek Olšák
2012-07-29 14:02 ` Marek Olšák [this message]
2012-07-29 17:04   ` [PATCH 2/2] radeon: optimize allocation for depth w/o stencil and stencil w/o depth on EG Marek Olšák
2012-07-30 14:56     ` Jerome Glisse
2012-07-30 15:17       ` Christian König
2012-07-30 15:22         ` Jerome Glisse
2012-07-30 15:37       ` Roland Scheidegger
2012-07-30 15:48       ` Marek Olšák
2012-07-30 16:03         ` Alex Deucher
2012-07-30 16:16           ` Alex Deucher
2012-07-30 16:52             ` Jerome Glisse
2012-07-30 17:03               ` Alex Deucher
2012-07-30 17:08                 ` Jerome Glisse
2012-07-30  8:29 ` [PATCH 1/2] radeon: simplify ZS buffer checking on r600 Christian König

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