From: Wang Xingchao <xingchao.wang@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: tiwai@suse.d, paulo.r.zanoni@intel.com
Subject: [PATCH v4 1/3] drm/i915: HSW audio registers definition
Date: Mon, 6 Aug 2012 18:43:58 +0800 [thread overview]
Message-ID: <1344249840-14700-2-git-send-email-xingchao.wang@intel.com> (raw)
In-Reply-To: <1344249840-14700-1-git-send-email-xingchao.wang@intel.com>
Add hsw audio registers definition
Signed-off-by: Wang Xingchao <xingchao.wang@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 48 +++++++++++++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1310caa..ed87de9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4277,6 +4277,54 @@
#define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16)
#define AUD_CONFIG_DISABLE_NCTS (1 << 3)
+/* HSW Audio */
+#define HSW_AUD_CONFIG_A 0x65000 /*Audio Configuration Transcoder A*/
+#define HSW_AUD_CONFIG_B 0x65100 /*Audio Configuration Transcoder B*/
+#define HSW_AUD_CFG(pipe) _PIPE(pipe, \
+ HSW_AUD_CONFIG_A, \
+ HSW_AUD_CONFIG_B)
+#define HSW_AUD_MISC_CTRL_A 0x65010 /*Audio Misc Control Convert 1*/
+#define HSW_AUD_MISC_CTRL_B 0x65110 /*Audio Misc Control Convert 2*/
+#define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \
+ HSW_AUD_MISC_CTRL_A, \
+ HSW_AUD_MISC_CTRL_B)
+
+#define HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 /*Audio DIP and ELD Control State Transcoder A*/
+#define HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 /*Audio DIP and ELD Control State Transcoder B*/
+#define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \
+ HSW_AUD_DIP_ELD_CTRL_ST_A, \
+ HSW_AUD_DIP_ELD_CTRL_ST_B)
+
+#define HSW_AUD_PIPE_CONV_CFG 0x6507c /*Audio pipe and converter configs*/
+#define HSW_AUD_PIN_ELD_CP_VL 0x650c0 /*Audio ELD and CP Ready Status*/
+#define AUDIO_INACTIVE_C (1<<11)
+#define AUDIO_INACTIVE_B (1<<7)
+#define AUDIO_INACTIVE_A (1<<3)
+#define AUDIO_OUTPUT_ENABLE_A (1<<2)
+#define AUDIO_OUTPUT_ENABLE_B (1<<6)
+#define AUDIO_OUTPUT_ENABLE_C (1<<10)
+#define AUDIO_ELD_VALID_A (1<<0)
+#define AUDIO_ELD_VALID_B (1<<4)
+#define AUDIO_ELD_VALID_C (1<<8)
+#define AUDIO_CP_READY_A (1<<1)
+#define AUDIO_CP_READY_B (1<<5)
+#define AUDIO_CP_READY_C (1<<9)
+
+/* Audio Digital Converter*/
+#define HSW_AUD_DIG_CNVT_1 0x65080 /*Audio Converter 1*/
+#define HSW_AUD_DIG_CNVT_2 0x65180 /*Audio Converter 1*/
+#define AUD_DIG_CNVT(pipe) _PIPE(pipe, \
+ HSW_AUD_DIG_CNVT_1, \
+ HSW_AUD_DIG_CNVT_2)
+
+#define HSW_AUD_EDID_DATA 0x65050
+
+#define TRANS_CONF_A 0xf0008
+#define AUD_PB_UNSL_DEV_CP 0x65fb0
+#define AUD_PC_UNSL_DEV_CP 0x65fb4
+#define AUD_PD_UNSL_DEV_CP 0x65fb8
+
+
/* HSW Power Wells */
#define HSW_PWR_WELL_CTL1 0x45400 /* BIOS */
#define HSW_PWR_WELL_CTL2 0x45404 /* Driver */
--
1.7.9.5
next prev parent reply other threads:[~2012-08-06 10:56 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-08-06 10:43 [PATCH v4 0/3] Haswell HDMI/DP audio enable Wang Xingchao
2012-08-06 10:43 ` Wang Xingchao [this message]
2012-08-07 12:54 ` [PATCH v4 1/3] drm/i915: HSW audio registers definition Paulo Zanoni
2012-08-06 10:43 ` [PATCH V4 2/3] drm/i915: write eld info for HDMI audio Wang Xingchao
2012-08-06 10:44 ` [PATCH v4 3/3] drm/i915: Haswell HDMI audio enable Wang Xingchao
2012-08-07 13:00 ` Paulo Zanoni
2012-08-06 14:26 ` [PATCH v4 0/3] Haswell HDMI/DP " Takashi Iwai
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