From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: linux-omap@vger.kernel.org,
Santosh Shilimkar <santosh.shilimkar@ti.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will.deacon@arm.com>,
Russell King <linux@arm.linux.org.uk>,
Nicolas Pitre <nicolas.pitre@linaro.org>,
Colin Cross <ccross@android.com>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Amit Kucheria <amit.kucheria@linaro.org>,
Dave Martin <dave.martin@linaro.org>,
Wenzeng Chen <wzch@marvell.com>
Subject: [RFC PATCH 3/6] ARM: mm: add v7 dcache level API
Date: Thu, 13 Sep 2012 11:20:48 +0100 [thread overview]
Message-ID: <1347531651-28218-4-git-send-email-lorenzo.pieralisi@arm.com> (raw)
In-Reply-To: <1347531651-28218-1-git-send-email-lorenzo.pieralisi@arm.com>
From: Santosh Shilimkar <santosh.shilimkar@ti.com>
On ARMv7 based SOC with an integrated L2 cache, there is a need
to have a flush API to operate on each cache level. In few low
power modes, L2 cache is retained whereas L1 is lost. The current
v7_flush_dcache_all(), flushes all the levels and it would be quite
expensive in cases where only one of the level needs to be flushed.
So this patch introduces v7_flush_dcache_level() API which takes a
parameter (cache level), and flush only that level.
This API is useful for the power management code where depending on CPU
and CPU cluster low power state, a specific cache level can be cleaned
instead of cleaning all the cache levels with existing flush_dcache_all().
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
---
arch/arm/mm/cache-v7.S | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 74aec79..d0fbe5c 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -51,6 +51,26 @@ ENTRY(v7_flush_dcache_louis)
b __flush_level
ENDPROC(v7_flush_dcache_louis)
+ /*
+ * v7_flush_dcache_level(level)
+ *
+ * Flush the D-cache the specified level passed as input parameter.
+ *
+ * r0 - cache level
+ *
+ * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
+ */
+
+ENTRY(v7_flush_dcache_level)
+ dmb @ ensure ordering with previous memory accesses
+ sub r10, r0, #1
+ mov r10, r10, lsl #1
+ movs r3, r0, lsl #1 @ level * 2
+ mrc p15, 1, r0, c0, c0, 1 @ read clidr
+ moveq pc, lr @ return if level == 0
+ b __flush_level
+ENDPROC(v7_flush_dcache_level)
+
/*
* v7_flush_dcache_all()
*
--
1.7.12
WARNING: multiple messages have this Message-ID (diff)
From: lorenzo.pieralisi@arm.com (Lorenzo Pieralisi)
To: linux-arm-kernel@lists.infradead.org
Subject: [RFC PATCH 3/6] ARM: mm: add v7 dcache level API
Date: Thu, 13 Sep 2012 11:20:48 +0100 [thread overview]
Message-ID: <1347531651-28218-4-git-send-email-lorenzo.pieralisi@arm.com> (raw)
In-Reply-To: <1347531651-28218-1-git-send-email-lorenzo.pieralisi@arm.com>
From: Santosh Shilimkar <santosh.shilimkar@ti.com>
On ARMv7 based SOC with an integrated L2 cache, there is a need
to have a flush API to operate on each cache level. In few low
power modes, L2 cache is retained whereas L1 is lost. The current
v7_flush_dcache_all(), flushes all the levels and it would be quite
expensive in cases where only one of the level needs to be flushed.
So this patch introduces v7_flush_dcache_level() API which takes a
parameter (cache level), and flush only that level.
This API is useful for the power management code where depending on CPU
and CPU cluster low power state, a specific cache level can be cleaned
instead of cleaning all the cache levels with existing flush_dcache_all().
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
---
arch/arm/mm/cache-v7.S | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 74aec79..d0fbe5c 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -51,6 +51,26 @@ ENTRY(v7_flush_dcache_louis)
b __flush_level
ENDPROC(v7_flush_dcache_louis)
+ /*
+ * v7_flush_dcache_level(level)
+ *
+ * Flush the D-cache the specified level passed as input parameter.
+ *
+ * r0 - cache level
+ *
+ * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
+ */
+
+ENTRY(v7_flush_dcache_level)
+ dmb @ ensure ordering with previous memory accesses
+ sub r10, r0, #1
+ mov r10, r10, lsl #1
+ movs r3, r0, lsl #1 @ level * 2
+ mrc p15, 1, r0, c0, c0, 1 @ read clidr
+ moveq pc, lr @ return if level == 0
+ b __flush_level
+ENDPROC(v7_flush_dcache_level)
+
/*
* v7_flush_dcache_all()
*
--
1.7.12
next prev parent reply other threads:[~2012-09-13 10:21 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-09-13 10:20 [RFC PATCH 0/6] ARM: augment cache flushing API Lorenzo Pieralisi
2012-09-13 10:20 ` Lorenzo Pieralisi
2012-09-13 10:20 ` [RFC PATCH 1/6] ARM: mm: define LoUIS API for cache maintenance ops Lorenzo Pieralisi
2012-09-13 10:20 ` Lorenzo Pieralisi
2012-09-13 11:39 ` Dave Martin
2012-09-13 11:39 ` Dave Martin
2012-09-13 13:03 ` Russell King - ARM Linux
2012-09-13 13:03 ` Russell King - ARM Linux
2012-09-13 14:02 ` Dave Martin
2012-09-13 14:02 ` Dave Martin
2012-09-13 12:36 ` Russell King - ARM Linux
2012-09-13 12:36 ` Russell King - ARM Linux
2012-09-13 12:57 ` Lorenzo Pieralisi
2012-09-13 12:57 ` Lorenzo Pieralisi
2012-09-13 10:20 ` [RFC PATCH 2/6] ARM: mm: add v7 cache LoUIS API implementation Lorenzo Pieralisi
2012-09-13 10:20 ` Lorenzo Pieralisi
2012-09-13 10:20 ` Lorenzo Pieralisi [this message]
2012-09-13 10:20 ` [RFC PATCH 3/6] ARM: mm: add v7 dcache level API Lorenzo Pieralisi
2012-09-13 10:20 ` [RFC PATCH 4/6] ARM: kernel: update cpu_suspend code to use cache LoUIS operations Lorenzo Pieralisi
2012-09-13 10:20 ` Lorenzo Pieralisi
2012-09-13 12:53 ` Dave Martin
2012-09-13 12:53 ` Dave Martin
2012-09-13 13:01 ` Shilimkar, Santosh
2012-09-13 13:01 ` Shilimkar, Santosh
2012-09-13 13:08 ` Russell King - ARM Linux
2012-09-13 13:08 ` Russell King - ARM Linux
2012-09-13 13:18 ` Shilimkar, Santosh
2012-09-13 13:18 ` Shilimkar, Santosh
2012-09-13 14:28 ` Lorenzo Pieralisi
2012-09-13 14:28 ` Lorenzo Pieralisi
2012-09-13 14:18 ` Lorenzo Pieralisi
2012-09-13 14:18 ` Lorenzo Pieralisi
2012-09-13 10:20 ` [RFC PATCH 5/6] ARM: kernel: update __cpu_disable to use cache LoUIS maintenance API Lorenzo Pieralisi
2012-09-13 10:20 ` Lorenzo Pieralisi
2012-09-13 10:20 ` [RFC PATCH 6/6] ARM: mm: update __v7_setup() to the new LoUIS cache " Lorenzo Pieralisi
2012-09-13 10:20 ` Lorenzo Pieralisi
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1347531651-28218-4-git-send-email-lorenzo.pieralisi@arm.com \
--to=lorenzo.pieralisi@arm.com \
--cc=amit.kucheria@linaro.org \
--cc=catalin.marinas@arm.com \
--cc=ccross@android.com \
--cc=daniel.lezcano@linaro.org \
--cc=dave.martin@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-omap@vger.kernel.org \
--cc=linux@arm.linux.org.uk \
--cc=nicolas.pitre@linaro.org \
--cc=santosh.shilimkar@ti.com \
--cc=will.deacon@arm.com \
--cc=wzch@marvell.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.