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From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: linux-omap@vger.kernel.org,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will.deacon@arm.com>,
	Russell King <linux@arm.linux.org.uk>,
	Nicolas Pitre <nicolas.pitre@linaro.org>,
	Colin Cross <ccross@android.com>,
	Santosh Shilimkar <santosh.shilimkar@ti.com>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Amit Kucheria <amit.kucheria@linaro.org>,
	Dave Martin <dave.martin@linaro.org>,
	Wenzeng Chen <wzch@marvell.com>
Subject: [RFC PATCH 5/6] ARM: kernel: update __cpu_disable to use cache LoUIS maintenance API
Date: Thu, 13 Sep 2012 11:20:50 +0100	[thread overview]
Message-ID: <1347531651-28218-6-git-send-email-lorenzo.pieralisi@arm.com> (raw)
In-Reply-To: <1347531651-28218-1-git-send-email-lorenzo.pieralisi@arm.com>

When a CPU is hotplugged out caches that reside in its power domain
lose their contents and so must be cleaned to the next memory level.

Currently, __cpu_disable calls flush_cache_all() that for new generation
processor like A15/A7 ends up cleaning and invalidating all cache levels
up to Level of Coherency, which includes the unified L2.

This ends up being a waste of cycles since the L2 cache contents are not
lost on power down.

This patch updates __cpu_disable to use the new LoUIS API cache operations.

Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
---
 arch/arm/kernel/smp.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index d3eb222..f44e9cd 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -136,8 +136,11 @@ int __cpu_disable(void)
 	/*
 	 * Flush user cache and TLB mappings, and then remove this CPU
 	 * from the vm mask set of all processes.
+	 *
+	 * Caches are flushed to the Level of Unification Inner Shareable
+	 * to write-back dirty lines to unified caches shared by all CPUs.
 	 */
-	flush_cache_all();
+	flush_cache_louis();
 	local_flush_tlb_all();
 
 	clear_tasks_mm_cpumask(cpu);
-- 
1.7.12



WARNING: multiple messages have this Message-ID (diff)
From: lorenzo.pieralisi@arm.com (Lorenzo Pieralisi)
To: linux-arm-kernel@lists.infradead.org
Subject: [RFC PATCH 5/6] ARM: kernel: update __cpu_disable to use cache LoUIS maintenance API
Date: Thu, 13 Sep 2012 11:20:50 +0100	[thread overview]
Message-ID: <1347531651-28218-6-git-send-email-lorenzo.pieralisi@arm.com> (raw)
In-Reply-To: <1347531651-28218-1-git-send-email-lorenzo.pieralisi@arm.com>

When a CPU is hotplugged out caches that reside in its power domain
lose their contents and so must be cleaned to the next memory level.

Currently, __cpu_disable calls flush_cache_all() that for new generation
processor like A15/A7 ends up cleaning and invalidating all cache levels
up to Level of Coherency, which includes the unified L2.

This ends up being a waste of cycles since the L2 cache contents are not
lost on power down.

This patch updates __cpu_disable to use the new LoUIS API cache operations.

Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
---
 arch/arm/kernel/smp.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index d3eb222..f44e9cd 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -136,8 +136,11 @@ int __cpu_disable(void)
 	/*
 	 * Flush user cache and TLB mappings, and then remove this CPU
 	 * from the vm mask set of all processes.
+	 *
+	 * Caches are flushed to the Level of Unification Inner Shareable
+	 * to write-back dirty lines to unified caches shared by all CPUs.
 	 */
-	flush_cache_all();
+	flush_cache_louis();
 	local_flush_tlb_all();
 
 	clear_tasks_mm_cpumask(cpu);
-- 
1.7.12

  parent reply	other threads:[~2012-09-13 10:21 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-09-13 10:20 [RFC PATCH 0/6] ARM: augment cache flushing API Lorenzo Pieralisi
2012-09-13 10:20 ` Lorenzo Pieralisi
2012-09-13 10:20 ` [RFC PATCH 1/6] ARM: mm: define LoUIS API for cache maintenance ops Lorenzo Pieralisi
2012-09-13 10:20   ` Lorenzo Pieralisi
2012-09-13 11:39   ` Dave Martin
2012-09-13 11:39     ` Dave Martin
2012-09-13 13:03     ` Russell King - ARM Linux
2012-09-13 13:03       ` Russell King - ARM Linux
2012-09-13 14:02       ` Dave Martin
2012-09-13 14:02         ` Dave Martin
2012-09-13 12:36   ` Russell King - ARM Linux
2012-09-13 12:36     ` Russell King - ARM Linux
2012-09-13 12:57     ` Lorenzo Pieralisi
2012-09-13 12:57       ` Lorenzo Pieralisi
2012-09-13 10:20 ` [RFC PATCH 2/6] ARM: mm: add v7 cache LoUIS API implementation Lorenzo Pieralisi
2012-09-13 10:20   ` Lorenzo Pieralisi
2012-09-13 10:20 ` [RFC PATCH 3/6] ARM: mm: add v7 dcache level API Lorenzo Pieralisi
2012-09-13 10:20   ` Lorenzo Pieralisi
2012-09-13 10:20 ` [RFC PATCH 4/6] ARM: kernel: update cpu_suspend code to use cache LoUIS operations Lorenzo Pieralisi
2012-09-13 10:20   ` Lorenzo Pieralisi
2012-09-13 12:53   ` Dave Martin
2012-09-13 12:53     ` Dave Martin
2012-09-13 13:01     ` Shilimkar, Santosh
2012-09-13 13:01       ` Shilimkar, Santosh
2012-09-13 13:08       ` Russell King - ARM Linux
2012-09-13 13:08         ` Russell King - ARM Linux
2012-09-13 13:18         ` Shilimkar, Santosh
2012-09-13 13:18           ` Shilimkar, Santosh
2012-09-13 14:28       ` Lorenzo Pieralisi
2012-09-13 14:28         ` Lorenzo Pieralisi
2012-09-13 14:18     ` Lorenzo Pieralisi
2012-09-13 14:18       ` Lorenzo Pieralisi
2012-09-13 10:20 ` Lorenzo Pieralisi [this message]
2012-09-13 10:20   ` [RFC PATCH 5/6] ARM: kernel: update __cpu_disable to use cache LoUIS maintenance API Lorenzo Pieralisi
2012-09-13 10:20 ` [RFC PATCH 6/6] ARM: mm: update __v7_setup() to the new LoUIS cache " Lorenzo Pieralisi
2012-09-13 10:20   ` Lorenzo Pieralisi

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