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From: Jesse Barnes <jbarnes@virtuousgeek.org>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 5/8] drm/i915: implement WaDisablePSDDualDispatchEnable on IVB & VLV
Date: Thu, 18 Oct 2012 10:43:48 -0500	[thread overview]
Message-ID: <1350575031-13534-5-git-send-email-jbarnes@virtuousgeek.org> (raw)
In-Reply-To: <1350575031-13534-1-git-send-email-jbarnes@virtuousgeek.org>

Workaround for dual port PS dispatch on GT1.

v2: pull in register definition & offset handling
v3: use IVB GT1 macro to get the right regs (Ben)
v4: add for VLV too (Ben)

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.c |    1 +
 drivers/gpu/drm/i915/i915_reg.h |    5 +++++
 drivers/gpu/drm/i915/intel_pm.c |   14 ++++++++++++++
 3 files changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 39282a4..6f03b26 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1131,6 +1131,7 @@ static bool IS_DISPLAYREG(u32 reg)
 
 	switch (reg) {
 	case GEN7_ROW_CHICKEN2:
+	case GEN7_HALF_SLICE_CHICKEN1:
 		return false;
 	default:
 		break;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ecb28be..12816bb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4268,6 +4268,11 @@
 #define GEN7_L3LOG_BASE			0xB070
 #define GEN7_L3LOG_SIZE			0x80
 
+#define GEN7_HALF_SLICE_CHICKEN1	0xe100 /* IVB GT1 + VLV */
+#define GEN7_HALF_SLICE_CHICKEN1_IVB	0xf100
+#define   GEN7_MAX_PS_THREAD_DEP		(8<<12)
+#define   GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE	(1<<3)
+
 #define GEN7_ROW_CHICKEN2		0xe4f4
 #define GEN7_ROW_CHICKEN2_GT2		0xf4f4
 #define   DOP_CLOCK_GATING_DISABLE	(1<<0)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4c86549..7864da3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3527,6 +3527,16 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
 		   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
 		   CHICKEN3_DGMG_DONE_FIX_DISABLE);
 
+	/* WaDisablePSDDualDispatchEnable */
+	if (IS_IVB_GT1(dev))
+		I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
+			   I915_READ(GEN7_HALF_SLICE_CHICKEN1) |
+			   _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
+	else
+		I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_IVB,
+			   I915_READ(GEN7_HALF_SLICE_CHICKEN1) |
+			   _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
+
 	/* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
 	I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
 		   GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
@@ -3615,6 +3625,10 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
 		   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
 		   CHICKEN3_DGMG_DONE_FIX_DISABLE);
 
+	I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
+		   I915_READ(GEN7_HALF_SLICE_CHICKEN1) |
+		   _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
+
 	/* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
 	I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
 		   GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
-- 
1.7.9.5

  parent reply	other threads:[~2012-10-18 15:43 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-10-18 15:43 [PATCH 1/8] drm/i915: implement WaDisableL3CacheAging on VLV Jesse Barnes
2012-10-18 15:43 ` [PATCH 2/8] drm/i915: implement WaDisableDopClockGatingisable on VLV and IVB Jesse Barnes
2012-10-18 15:43 ` [PATCH 3/8] drm/i915: implement WaForceL3Serialization " Jesse Barnes
2012-10-18 15:43 ` [PATCH 4/8] drm/i915: implement WaDisableVLVClockGating_VBIIssue on VLV Jesse Barnes
2012-10-18 15:43 ` Jesse Barnes [this message]
2012-10-18 15:43 ` [PATCH 6/8] drm/i915: TLB invalidation with MI_FLUSH_SW requires a post-sync op Jesse Barnes
2012-10-18 15:43 ` [PATCH 7/8] drm/i915: PIPE_CONTROL TLB invalidate requires CS stall Jesse Barnes
2012-10-18 15:43 ` [PATCH 8/8] drm/i915: add clock gating regs to VLV offset check function Jesse Barnes
2012-10-18 18:07 [PATCH 1/8] drm/i915: implement WaDisableL3CacheAging on VLV Jesse Barnes
2012-10-18 18:07 ` [PATCH 5/8] drm/i915: implement WaDisablePSDDualDispatchEnable on IVB & VLV Jesse Barnes
2012-10-25 19:15 [PATCH 1/8] drm/i915: implement WaDisableL3CacheAging on VLV Jesse Barnes
2012-10-25 19:15 ` [PATCH 5/8] drm/i915: implement WaDisablePSDDualDispatchEnable on IVB & VLV Jesse Barnes

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